SAMA5 DMA: Need to flush caches; DMA channel depends upon direction of DMA; the maximum transfer size in bytes depends on the number of bytes per transfer
SAMA5: Use RDR/TDR registers for DMA, not FIFO registers; change DMA bit settings to match Atmel example.  Still no DMA
SAM3,4,A5 DMA fixes; SAMA5 SPI driver now supports DMA transfers
Fix some cache-related issues with the SAMA5 DMA driver
SAMA5:  Centralize logic for conversion between physical and virtual addresses
Extend the virtual-to-physical address conversion logic to handle NFS SRM, UDPH SRAM, and external SRAM and PSRAM.
Rearrange configuration settings so that ARCH_HAVE_SDIO is moved to higher, sharable level
Remove some pre-processor warnings that I am more than tired of seeing
SAMA5: Fix HSMCI race condition.  Now memory card interface is functional with DMA
MMC/SD SDIO:  Correct return values when multiple block transfers are suppressed.  From Andrew Tridgell via Lorenz Meier
Serial FIONREAD, FIONWRITE, and TERMIOS I/O processing from Mike Smith, Andrew Tridgell, and and Lorenz Meier
Added FIONREAD and FIONWRITE to CDC/ACM driver.  From Lorenz Meier
Added option to disable STM32 serial port re-ordering
STM32: Fix STM32 serial init for non-reordered serial ports.  From Lorenz Meier
Add CAN configuration to STM32 config menu
SAMA5:  Some improvements to the HSCMI card removal/insertion logic
Add untested OHCI driver for the SAMA5; structure naming and header files for USB host initialization prototypes
SAMA5:  Add support for initialization of the USB host and mass storage class