ARM: decompressor: avoid speculative prefetch from non-RAM areas

We setup identity MMU mappings across the entire 4GB of space, which
are permissionless because the domain is set to manager.

This unfortunately allows ARMv6 and later CPUs to speculatively
prefetch from the entire address space, which can cause undesirable
side effects if those regions contain devices.

As we setup the mappings with read/write permission, we can switch
the domain to client mode, and then use the XN bit for ARMv6 and
above to control speculative prefetch to non-RAM areas.

CRs-Fixed: 415757
Change-Id: I24bacf244b1e987e1b966eee64a2578cbdb12080
Reported-by: R Sricharan <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 3463f07a22f288c6230aa8c230f623d9183c5a10)

Signed-off-by: Shruthi Krishna <skrish@codeaurora.org>
Disable ak8975 driver in iio
Move wlan gpio init to broadcom_wlan.c

Conflicts:
	arch/arm/mach-msm/board-ariesve.c
cpufreq: interactive: allow arbitrary speed / delay mappings

Accept a string of delays and speeds at which to apply the delay before
raising each step above hispeed. For example, "80000 1300000:200000
1500000:40000" means that the delay at or above 1GHz, until 1.3GHz is 80 msecs,
the delay until 1.5GHz is 200 msecs and the delay at or above 1.5GHz is 40
msecs when hispeed_freq is 1GHz.

[toddpoynor@google.com: add documentation]
Change-Id: Ifeebede8b1acbdd0a53e5c6916bccbf764dc854f
Signed-off-by: Minsung Kim <ms925.kim@samsung.com>
cpufreq: interactive: fix crash on error paths in get_tokenized_data

Use separate variable for error code, free proper pointer.

Change-Id: Ia83cccb195997789ac6afbf5b8761f7b278196d6
Reported-by: Arve Hjønnevåg <arve@android.com>
Signed-off-by: Todd Poynor <toddpoynor@google.com>
cpufreq: interactive: base above_hispeed_delay on target freq, not current

Time to wait should be based on the intended target speed, not the
actual speed (which may be held high by another CPU).

Change-Id: Ifc5bb55d06adddb9a02af90af05398a78f282272
Reported-by: Arve Hjønnevåg <arve@android.com>
Signed-off-by: Todd Poynor <toddpoynor@google.com>
Revert "msm_fb: display: remove background invert alpha option for alpha drop pipe"

This reverts commit 0119007a18aae8a8fb43f4320509bda161da4167.

CRs-fixed: 461574
Change-Id: Ia768030ec859a4ff38549686936789413826df32
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
msm_fb: display: silent blending error warning message

If there had no any pipe blending stage changes, then do not
call belnding set up to avoid unnecessary warning messges.

CRs-fixed: 467556
Change-Id: I07520b3b0917375c41405e736dcb9eb8a3daddc1
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
msm_fb: display: exit properly when rotator max session reached

When rotator session reach maximum, it should exit without calling
put_img since no get_img had been called.

CRs-fixed: 466462
Change-Id: I951570227ebd81da6dad19c1b897cde84f8d0451
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
msm_fb: Fix adb shell start/stop issue when bypass enabled

Currently when 2/3/4 layer bypass is enabled, doing a adb shell
stop/start is failing overlay and composition happens through
GPU. Fix this issue by proper overlay configuration during this
scenario.

Change-Id: Ia04f1839bf80ed552671e48445af63a4dcd6bdfd
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
msm: smd: Refactor init code for platform data

Refactor init code to use configuration data from
platform devices. Platform device will contain the
interrupt numbers and other configurations
that is valid for a particular target. SMD init code
will use the platform data to register for and trigger
the interrupts which are relevant to a target.

Signed-off-by: Angshuman Sarkar <angshuman@codeaurora.org>
(cherry picked from commit bad32df37b5b1a68eef81f9c004c6138d5c3a739)

Change-Id: Ic95075856a17dac031cec2cea205736cbeb92e46
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
msm: board: share the same ADM channel between NAND and eMMC

Currently for MSM7x27A and MSM7x30, all the SDCC slots share
the same ADM channel. This means both SD and eMMC card slots
will share the same ADM channel. But as SD card can be hot pluggable,
SD card insertion/removal can cause the ADM channel flush which
possibly can affect the ongoing transfer on eMMC (as it shares the
same ADM channel with SD card).

On the other hand, we generally have either eMMC or NAND flash device
active on any platform. So if eMMC is used, NAND won't be used or
mostly not present on board. This means eMMC slot can use the same
ADM channel which NAND uses and this way both SD and eMMC slots will
have separate ADM channel.

CRs-fixed: 374842
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
(cherry picked from commit f29aefdd29f3add555d119f814ed209c8e455374)

Change-Id: I8cd05cd7d3b914f7de1f38146ca14eb4a08c6c57
Signed-off-by: Srivalli Oguri <oguri@codeaurora.org>
msm: board: Set the correct 2D core clock frequency in 7x30

The 2D clock was synchronously tied to the AXI bus in frequency on
the 7x30 platform. So its was never set before. Now, with the
updated clock APIs, this made the clock to be enabled before it is
prepared. This change ensures the clock is prepared before it is
enabled.

CRs-fixed: 375424
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>
(cherry picked from commit a89ffc7fbe30b3a16a8f77482c5942b9d08f314b)

Change-Id: Ibdf36c6b8202fb52425110d94de867b46f28a738
Signed-off-by: Gopal G Goberu <ggober@codeaurora.org>
msm: kgsl: Make use of the new clock APIs.

Use the split clock APIs to do low latency actions (enable/disable)
frequently.  Use the high latency functions (prepare/unprepare)
sparingly to help performance.

CRs-fixed: 351696
Change-Id: Iaf9ed2117a1647e38be8658c60a365d377c968a4
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
msm: kgsl: Ensure correct enable sequence for 2D core clock

Calling clk_set_rate() for both AXI & 2D core clocks without putting
them in async mode causes 2D core hang. Since AXI & 2D core clocks
are in sync mode, ensure that clk_set_rate() is called only for AXI
& 2D core clock is enabled only after it is prepared.

Change-Id: I4634e2342d62ce16ad7afc748b10b0573fbfd913
CRs-fixed: 385393
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
msm: kgsl: Resolve a potential race in the interrupt handler

In the GPU interrupt handler we attempt to clear the ts_cmp_enable
for the active context so that future interrupts are skipped until
someone needs one again. If for some reason the interrupt handler
is delayed then there is a possiblity that the "current" context in
the GPU isn't the one that fired the interrupt. In that case we
could be accidently clearing a ts_cmp_enable for a context that
needs it. Instead of clearing in the interrupt handler clear it
from the GPU so we can be sure we got the right context.

As a bonus pushing this logic to the GPU side lets us get rid of
some extra register reads/writes in the interrupt handlers.

Change-Id: I3cb3d1a3c626d0594e55bff4535990c1402764fa
Signed-off-by: Harsh Vardhan Dwivedi <hdwivedi@codeaurora.org>
msm: kgsl: Check the current interrupt status before power operations

Sometimes the core will go idle before the interrupt can be handled on
the GPU. If that happens then we could go to a lower power state before
cleaning up the pending interrupt and various entities that might be
waiting for it. Consider the current interrupt status when checking
for idle.

Change-Id: Idd43e56e0162a522e0929df83531aff94beadc19
Signed-off-by: Harsh Vardhan Dwivedi <hdwivedi@codeaurora.org>
msm: kgsl: Increase REG_RBBM_CNTL value to 0xFFFF for A200

Increase number of clocks that RBBM will wait before de-asserting
the Register Clock Active signal. This fixes kernel panics during
stability tests on multiple devices

Change-Id: I50ad69f28b50444e88239c2332bd5756db1ae089
CRs-fixed: 372793
Signed-off-by: Rammohan Basavaraju <rammoh@codeaurora.org>
msm: kgsl: Add TLB flush for each submit in case of 8x25/7x2xa

Add TLB flush for each submit to prevent target freeze
in case of 8x25/7x27a/7x25a targets.

CRs-fixed: 379991
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
(cherry picked from commit 22a06d18c6eb100419616ddf7a2c4ac403420a9e)

Change-Id: I7c34660128c791c9329b41246af39879625d64d3
Signed-off-by: Srivalli Oguri <oguri@codeaurora.org>
msm: kgsl: use correct 2d ringbuffer offset in resume

The 2d timestamp is used as an index into the ringbuffer.
Now that z180_dev->current_timestamp is preserved across
resume, make sure that ADDR_VGV3_NEXTADDR is set to the
gpu address that corresponds to the current timestamp.

CRs-Fixed: 347025
Change-Id: Ib7dc4579943ab24e04279ede1555539ec21adabd
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>