msm: pm2: Write a known pattern before enter into LPM

Write a known pattern before enter into LPM mode.
Currently these markers are added to log the cores
warmboot entry locations and default value set to 0x0.
Change the default value to a known value instead of 0x0.

Change-Id: I31b4a985074eea4b7f9970518a48138620f582e9
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
Merge "msm: pm2: Write a known pattern before enter into LPM"
arm: Kconfig: Disable CONFIG_OABI_COMPAT feature on SMP targets

When this option is enabled to support Old ABI, it introduces
a race condition in swap-out code on SMP, such that
instruction is available to the instruction stream (SWI
instruction) but not the data stream.

CPU0		CPU1
clears pte
		executes instruction from page,
		already has I-TLB but no D-TLB entry,
		takes SWI exception
		tries to load instruction, data abort
tlb flush

Therefore, disable this feature on SMP targets.

Change-Id: I4cc4e6924cfcffad391fe2e68d5aa62eee613b0e
Signed-off-by: Jay Chokshi <jchokshi@codeaurora.org>
msm: restart_7k: Disable local IRQ interrupt

While doing the power on/off test, there is a chance
where APPS proc can receive the proc comm interrupt from
the modem. But at this stage proc comm channels are
already disabled and can't handle any new proc comm
requests that are coming in. Hence disable the local
interrupts.

Change-Id: If80928e69ae0d1522b0da186e075142122d9558d
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Merge "arm: Kconfig: Disable CONFIG_OABI_COMPAT feature on SMP targets"
Merge "msm: restart_7k: Disable local IRQ interrupt"