Drop unnecessary execution permission for .cpp/.c/.h

Change-Id: I9ac2b9d8f6bdb4fab8962210c5ec8f9c3e8c0ebf
Drop magic number in strrchr and strchr

Change-Id: Ic7391be8575eaaac76914dab62bc41c9773d703d
Adding strcmp tuned for Cortex-A15.

The attached patch provides a new implementation of strcmp for ARM,
using LDRD instead of LDR whenever possible.

For older architectures that do not support LDRD, this implementation
uses the same algorithm as before.

Testing and benchmarking:
* Validation: successfully passes a test that compares different strings
of length 1-128 and offsets 0-8 from a word boundary. Checked on
qemu/A15/A9, ARM/Thumb mode, Big/Little Endian.
* Integration with gcc: no regression on qemu for arm-none-eabi --with-cpu
a15/a9 --with-mode arm/thumb.

Change-Id: I9e230e1b99dbdc9119b69ee858a89038c516a4ea
Signed-off-by: Vassilis Laganakos <vasileios.laganakos@arm.com>
Adding memcpy tuned for Cortex-A15.

The strategy for large block sizes is LDRD and STRD with offset addressing,
where the main loop copies 64 bytes in every iteration, (i.e., 8 calls to
LDRD and STRD pairs), interleaving load and stores (i.e., the pairs of LDRD
and STRD of the same data are consecutive instructions), and the writeback
of an updated address is a separate instruction, which allows us to write
back the accumulated update once per iteration.

This strategy is implemented in memcpy.S. In some configurations, a plain
version of memcpy (included from memcpy-stub.c) is used instead of the
optimized one.

Validation:
* Correctness: checked memcpy using a test harness for block sizes
ranging between 1 to 128, and source and destination buffers alignment
ranging in { 0,1,2,3,4,8,12 } bytes each.
* Performance: benchmarking on Cortex-A15 FPGA indicates that this strategy
is better for A15 than the strategy used by glibc and even slightly better
than using NEON. Benchmarking on Cortex-A9 bare metal and Linux shows
that the proposed strategy is reasonable: not as fast as the version of
memcpy from glibc (which is the best open source strategy for A9), but
comparable with csl and bionic.
* Integration with GCC: no regression for arm-none-eabi --with-cpu
cortex-a15 and cortex-a9.

Change-Id: Ied56354d8992c62ae3e02d582a2bd55585d814b9
Signed-off-by: Vassilis Laganakos <vasileios.laganakos@arm.com>
Add stack unwinding directives to memcpy.

Also include some Android specific header files.

Change-Id: Idbcbd43458ba945ca8c61bfbc04ea15fc0ae4e00
do not build or enable pthread debug

Conflicts:
	libc/Android.mk

Change-Id: Ia5c15163b35d7395e1335471e90728077c39e2a1