pronto cpu: tie off decode inputs for MMU exceptions as we don't have one
espresso cpu: tie off decode inputs for MMU exceptions as we don't have one
espresso and pronto ctrl: fix bugs with simultaneous tick and IRQ exceptions
There were two situations where simultaneous tick and IRQ exceptions were not behaving correctly.
One was where returning from an IRQ exception with a waiting tick exception, the IRQ exception vector address was put onto the bus instead of the tick address.
The second was a bug to do with with, again, returning from exception from a tick or IRQ exception when the other was waiting. Instead of the EPCR remaining the same (just like if exception had gone on to continue but again vectored to the exception handler) the EPCR was getting set to the handler address we just l.rfed from.