Fix some interconnect bugs exposed by introducing async bridge:
- When looking to see if a write burst data transfer is finished, look at the master signals, not slave 0 (SRAM). This made it work incorrectly when accessing SDRAM.
- Make wvalid/wready/awvalid/awready signals dependent on write state so we don't end up with extra transactions.
Break FPGA configuration into two clock domains: a memory clock and slower core clock.
This is in preparation for enabling a VGA controller.  The faster memory clock is necessary to support the memory bandwidth required by the display, but the CPU has an Fmax of ~30Mhz.
Remove unneeded file