video: tegra: host: Support multiple mem types

Support multiple memory handle types.

Change-Id: Ieae49d93be88616dde2498da98c66671cb3090a3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/135085
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
video: tegra: clean up memory alloc code paths
video: tegra: implement sg_table using DMA addresses
video: tegra: host: Pin each gather only once

Pin each gather only once. For each gather pinned, we copy the
acquired address to the rest of the gathers with the same memory
handle.

Change-Id: I47442cd5a167042b12a7fb4760a7ef0b83bdb9bd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/139301
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Tested-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
video: tegra: disable sync points
timekeeping: Fix time moving backwards

Changed the calculation logic that sometimes calculates
the time wrong.

Sometimes there is an overflow when the tv_nsec field in
the timespec structure is being added since it is 32-bit.

To resolve this issue nsec variable is being added first
so that the addition is performed in 64 bit signed format.

Bug 1217429

Change-Id: I9c65da88f02596ba73c47be6342ed909e650db22
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/195092
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Shridhar Rasal <srasal@nvidia.com>
video: tegra: use module id from hw headers
video: tegra: add header for defining classids
video: tegra: also use hw headers for methods