drm/nvc0-/gr: pull out a group of separately context-switched gpc regs

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nve0-/gr: some new gpc registers can have multiple copies

GK110 exposes more than one, and needs to be dealt with in the ctxsw
ucode just like the TPC sets are.

Broadcast is at +0xe00.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvc0-/gr: tpc regs a subset of gpc, add separate list for gpc/unk regs

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvc0-/gr: generate cs register lists from grctx data

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvd7/gr: initial support

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvf0/fifo: enable support

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvf0/ce: enable support

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvf0/gr: magic sequence that makes PGRAPH come out of hiding

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvf0/gr: enable support, if external cs ucode is available

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvc0/devinit: minor typo

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvf0/gr: fix ddx shaders locking up on me

This can be generalised and used on GK104 (probably even GF117), but lets
just make it work for now.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvc0-/gr: extend one of the magic calculations for >4 GPCs

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvf0/gr: build cs ucode for GK110

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvc0-/gr: remove hardcoding of UNK count/mask in GPCCS ucode

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvf0-/gr: ctxsw scratch reg count got bumped to 16

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvd7/devinit: use fermi class, not tesla

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvc0-/gr: factor out yet more unknown magic into versioned functions

NVC1/NVD9 are the only chipsets that should have anything different
happen on them after this.  We previously weren't doing these
register modifications, and NVIDIA do.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nvc0-/gr: remove some more of the hardcoded register writes

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nouveau: use vmalloc for pgt allocation

Page tables on nv50 take 48kB, which can be hard to allocate in one piece.
Let's use vmalloc.

Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
Cc: stable@vger.kernel.org [3.7+]
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nv50-/disp: Use output specific mask in interrupt

The commit

   commit 476e84e126171d809f9c0b5d97137f5055f95ca8
   Author: Ben Skeggs <bskeggs@redhat.com>
   Date:   Mon Feb 11 09:24:23 2013 +1000

       drm/nv50-/disp: initial supervisor support for off-chip encoders

changed the write mask in one of the interrupt functions for on-chip encoders,
causing a regression in certain VGA dual-head setups. This commit reintroduces
the mask thus resolving the regression

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66129
Reported-and-Tested-by: Yves-Alexis <corsac@debian.org>
Cc: stable@vger.kernel.org [3.9+]
CC: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>