start of integration of common bus into CPLD
updates to local project paths
add README
I have no idea
added board routing
implement control logic for register memory
small
start to the SPI mods
rearranging libraries
Merge branch 'integration' into spi
working against fpga
first shot as fitting the logic into CPLD
jammed SPI stuff into CPLD
start of new schematic and board layout
fit all of the control code, added dirty indicator and external interrupt.
revamped schematic
new board layout
updates for v1.3 board
experiments with different hardware configurations.  This one moves everything into the chip except memory.
minor edits