add a verilog lint target to the generated Makefile
inlined pcie_7x_v2_1_core_top
inlined pcie_7x_0_pcie_top
inlined pcie_7x_0_axi_basic_top
inlined pcie_7x_0_axi_basic_rx
inlined pcie_7x_0_axi_basic_rx_pipeline
inlined pcie_7x_0_axi_basic_rx_null_gen
inlined pcie_7x_0_axi_basic_tx
inlined pcie_7x_0_axi_basic_tx_pipeline
inlined pcie_7x_0_axi_basic_tx_thrtl_ctl
added k7echo target
inlined pcie_7x_0_pcie_7x
inlined pcie_7x_0_pcie_pipe_pipeline
split eof bits out of s_axis_rx_tuser
split sof and hit from tuser
removed V6- and S6-specific code
removed code for C_PM_PRIORITY == "TRUE"
export trn_rd
moved rx pipeline to BSV
moved TX interface to BSV