Fix <uchar.h> in for C++11.

It turns out that in C++11, char16_t and char32_t are built-in types;
language keywords. Just fix this by putting traditional _*_T_DECLARED
blocks around the definitions. We'll just predefine these in
<sys/_types.h>.

This also opens up the possibility to define char16_t in other header
files, if ever needed (e.g. if we would gain a <ctype.h> for
char16_t/char32_t).
Fix some statical clang analyzer warnings.
Add missing #includes, to keep Clang silent.
Add C11 macros CMPLX(), CMPLXF() and CMPLXL().

Clang allows us to initialize complex numbers using an array
initializer, casted to a complex type. GCC has a builtin called
__builtin_complex().
Make the malloc(3) family of functions weak and make their non-weak
implementations visible for use by applications. The functions $F that
are now weak symbols are:
	allocm, calloc, dallocm, free, malloc, malloc_usable_size,
	nallocm, posix_memalign, rallocm, realloc, sallocm

The non-weak implementations of $F are exported as __$F.

Submitted by:	stevek@juniper.net
Reviewed by:	jasone@, kib@
Approved by:	jasone@ (jemalloc)
Obtained from:	juniper Networks, Inc
Rework the comment I initially wrote when SHLIB_LDSCRIPT was introduced.
The build system is really intricate and I had a hard time to remind the
whole picture even when reading my own words.  This one will hopefully
be better.
Move libmd.so.5 to the proper place and add missing lib32 entry.
Pull in r182656 from upstream llvm trunk:

  LoopVectorize: LoopSimplify can't canonicalize loops with an
  indirectbr in it, don't assert on those cases.

  Fixes PR16139.

This should fix clang assertion failures when optimizing at -O3, similar
to:

  Assertion failed: (TheLoop->getLoopPreheader() && "No preheader!!"),
  function canVectorize, file
  contrib/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp, line 2171.

Reported by:	O. Hartmann <ohartman@zedat.fu-berlin.de>
PR:		ports/178332, ports/178977
MFC after:	3 days
Remove backwards compat layer which was added in r71419 (in 2001).

This change is not intended for MFC.

Reviewed by:	peter
s/recieve/receive
Unbreak ia64 tinderbox: 64-bit support was made conditional upon
__amd64__, and thus limited. Eliminate 2 trivial conditionals by
casting the 64-bit integral, holding an address, via (uintptr_t)
to (void *) and replace the last remaining check for __amd64__
with a check for __LP64__ instead.
Migrate ath(4) to now use if_transmit instead of the legacy if_start
and if queue mechanism; also fix up (non-11n) TX fragment handling.

This may result in a bit of a performance drop for now but I plan on
debugging and resolving this at a later stage.

Whilst here, fix the transmit path so fragment transmission works.

The TX fragmentation handling is a bit more special.  In order to
correctly transmit TX fragments, there's a bunch of corner cases that
need to be handled:

* They must be transmitted back to back, in the same order..
* .. ie, you need to hold the TX lock whilst transmitting this
  set of fragments rather than interleaving it with other MSDUs
  destined to other nodes;
* The length of the next fragment is required when transmitting, in
  order to correctly set the NAV field in the current frame to the
  length of the next frame; which requires ..
* .. that we know the transmit duration of the next frame, which ..
* .. requires us to set the rate of all fragments to the same length,
  or make the decision up-front, etc.

To facilitate this, I've added a new ath_buf field to describe the
length of the next fragment.  This avoids having to keep the mbuf
chain together.  This used to work before my 11n TX path work because
the ath_tx_start() routine would be handed a single mbuf with m_nextpkt
pointing to the next frame, and that would be maintained all the way
up to when the duration calculation was done.  This doesn't hold
true any longer - the actual queuing may occur at any point in the
future (think ath_node TID software queuing) so this information
needs to be maintained.

Right now this does work for non-11n frames but it doesn't at all
enforce the same rate control decision for all frames in the fragment.
I plan on fixing this in a followup commit.

RTS/CTS has the same issue, I'll look at fixing this in a subsequent
commit.

Finaly, 11n fragment support requires the driver to have fully
decided what the rate scenario setup is - including 20/40MHz,
short/long GI, STBC, LDPC, number of streams, etc.  Right now that
decision is (currently) made _after_ the NAV field value is updated.
I'll fix all of this in subsequent commits.

Tested:

* AR5416, STA, transmitting 11abg fragments
* AR5416, STA, 11n fragments work but the NAV field is incorrect for
  the reasons above.

TODO:

* It would be nice to be able to queue mbufs per-node and per-TID so
  we can only queue ath_buf entries when it's time to assemble frames
  to send to the hardware.

  But honestly, we should just do that level of software queue management
  in net80211 rather than ath(4), so I'm going to leave this alone for now.

* More thorough AP, mesh and adhoc testing.

* Ensure that net80211 doesn't hand us fragmented frames when A-MPDU has
  been negotiated, as we can't do software retransmission of fragments.

* .. set CLRDMASK when transmitting fragments, just to ensure.
Add clock definitions for LCD controller and PWM module
Add SCM registers definitions for AM335x platform
Add PWM module driver for AM335x. Only eCAS subsystem is supported

Export function to configure eCAS submodule from another drivers.
It's used to control LCD panel backlight on AM335x EVM.
AM335x LCD controller driver with syscons support

Limitations:
- Raster mode only
- 24 and 32 bpp only
Add PWM and LCDC nodes to base DTS for AM335x-based devices
Add DTS for AM335x EVM with properly muxed PWM and LCD pins, and
LCD panel description
Fix ONFI chip detection.

Submitted by:	Alexander Fedorov <alexander.fedorov@rtlservice.com>
Workaround for for a problem seen with ATI Technologies EHCI
controller hardware most likely present on UHCI chipsets aswell. The
bug manifests itself when issuing isochronous transfers and bulk
transfers towards the same device simultaneously. From time to time it
happens that either the completion IRQ was missing or that the
completion IRQ was happening before the ITD/SITD was completely
written back to memory. The workaround assumes that double buffered
isochronous transfers are used, and that a second interrupt is
generated at the beginning of the next isochronous transfer to
complete the previous one. Possibly skipping the interrupt at the last
isochronous frame is possible, but will then break single buffered
isochronous transfers. For now we can live with some extra interrupts.

MFC after:	1 week