Revert "LoopVectorize: Use the dependence test utility class"

This reverts commit cbfa1ca993363ca5c4dbf6c913abc957c584cbac.

We are seeing a stage2 and stage3 miscompare on some dragonegg bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184690 91177308-0d34-0410-b5e6-96231b3b80d8
DebugInfo: add some testing from an overly broad end-to-end test in Clang

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184692 91177308-0d34-0410-b5e6-96231b3b80d8
DebugInfo: enumerator values returned as int64 as they are stored

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184694 91177308-0d34-0410-b5e6-96231b3b80d8
Filter out dragonegg when checked out into a projects subdirectory.
There is some hope of eventually supporting a unified build with it, but
until then this lets me (and others) check it out in this location
without things breaking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184697 91177308-0d34-0410-b5e6-96231b3b80d8
Add a flag to defer vectorization into a phase after the inliner and its
CGSCC pass manager. This should insulate the inlining decisions from the
vectorization decisions, however it may have both compile time and code
size problems so it is just an experimental option right now.

Adding this based on a discussion with Arnold and it seems at least
worth having this flag for us to both run some experiments to see if
this strategy is workable. It may solve some of the regressions seen
with the loop vectorizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184698 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: enable decoding of pc-relative PLD/PLI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184701 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: fix IT decoding

mask == 0 -> UNPRED

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184702 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: fix thumb1 nop decoding

In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8.
However the disassembler should not use this alias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184703 91177308-0d34-0410-b5e6-96231b3b80d8
Temporarily enable MI-Sched on X86.

Sorry for the unit test churn. I'll try to make the change permanently
next time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184705 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: rGPR is meant to be unpredictable, not undefined

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184706 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: check predicate bits for thumb instructions

When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and
core registers, must have their predicate bit to 0b1110.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184707 91177308-0d34-0410-b5e6-96231b3b80d8
Add -mcpu to some unit tests that only fail on certain hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184709 91177308-0d34-0410-b5e6-96231b3b80d8
[APFloat] Rename macro convolve => PackCategoriesIntoKey so that it is clear what APFloat is actually using said macro for.

In the context of APFloat, seeing a macro called convolve suggests that APFloat
is using said value in some sort of convolution somewhere in the source code.
This is misleading.

I also added a documentation comment to the macro.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184710 91177308-0d34-0410-b5e6-96231b3b80d8
[APFloat] Removed a assert from significandParts() which says that one can only access the significand of FiniteNonZero/NaN floats.

The method significandParts() is a helper method meant to ease access to
APFloat's significand by allowing the user to not need to be aware of whether or
not the APFloat is using memory allocated in the instance itself or in an
external array.

This assert says that one can only access the significand of FiniteNonZero/NaN
floats. This makes it cumbersome and more importantly dangerous when one wishes
to zero out the significand of a zero/infinity value since one will have to deal
with the aforementioned quandary related to how the memory in APFloat is
allocated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184711 91177308-0d34-0410-b5e6-96231b3b80d8
[APFloat] Added make{Zero,Inf} methods and implemented get{Zero,Inf} on top of them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184712 91177308-0d34-0410-b5e6-96231b3b80d8
[APFloat] Added support for parsing float strings which contain {inf,-inf,NaN,-NaN}.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184713 91177308-0d34-0410-b5e6-96231b3b80d8
[APFloat] Added a large unittest for APFloat.add that checks that special values are computed correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184714 91177308-0d34-0410-b5e6-96231b3b80d8
[APFloat] Removed trailing whitespace from unittests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184715 91177308-0d34-0410-b5e6-96231b3b80d8
 This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184716 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] Support blrl and variants in the asm parser

This patch adds support for blrl and its conditional variants.
The patterns are (currently) used for the asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184718 91177308-0d34-0410-b5e6-96231b3b80d8