OMAPDSS: drop small YUV encoded frames on OMAP44xx

OMAP44xx has hardware limitation: in stall mode, when the frame pixel size
is less than output SyncFifo depth(16), DISPC hangs without sending any data.
Simple workaround is to drop such frame, as cases when YUV frames of this size
are very rare.

Change-Id: I31dc262b07a52b66209c093f136ad2bac66f9439
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
ARM: OMAP4460: Fixed missing dependency map of OPP for iva

Added missing dependency map of OPP-Nitro and OPP-SpeedBin for iva.
Without this line setting IVA into high OPP fail with errors:

rpres iva.0: _dep_scan_table: 1375000 volt map missing in vdd_core
rpres iva.0: omap_device_scale: Error in scan domains for vdd_iva

Change-Id: I73df4897e886a2d4c9fa22abcbc8a6f34c2a8503
Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com>
Signed-off-by: Amperific <amperific@gmail.com>

Conflicts:
	arch/arm/mach-omap2/opp4xxx_data.c

Conflicts:
	arch/arm/mach-omap2/opp4xxx_data.c
Revert "ARM: OMAP4460: Fixed missing dependency map of OPP for iva"

This reverts commit 1902bded7f423d617c5a0e735709139ab95e2cdb.

Signed-off-by: Amperific <amperific@gmail.com>

Conflicts:
	arch/arm/mach-omap2/opp4xxx_data.c
opp4xxx_data.c: Fix derp

Signed-off-by: Amperific <amperific@gmail.com>
power: decrease the amount of time the device waits after entering low power mode to freeze processes. Testing phase at the moment.

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
OMAPDSS: DISPC: fix pclk divisor limits

According to TRM, minimal pixel clock divisor value can be 1.
Fix corresponding checks, as high resolution panels use undivided
pixel clock frequency.

Also certain scaler unit constraint must be met: in case DISPC_CLK
and pixel clock frequencies are equal, set IPC to work on rising edge.

Change-Id: Iabeac2ad81f6909213cb81f4e16b1d0762369b53
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Dima Svetlov <svetlov@ti.com>
OMAPDSS: DISPC: more precise scale limits checking

Use division with rounding-up when checking if maximum downscale ratio
was reached. This allows to avoid SYNC_LOST errors in case when small
amount of extra pixels or lines (usually 1-3) not taken into account

Change-Id: Id8f88c64671146a64738cfd820378bb7a28c1455
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
fs/suspend_fstrim.c: use u64 instead of long; only measure screen-on-time; trim already after 6 minutes screen-on time
Linux 3.0.75
Add assembler versions of AES and SHA1 for ARM platforms.  This has provided
up to a 50% improvement in IPsec/TCP throughout for tunnels using AES128/SHA1.
ARMv7: Flush the vectors page using the base address

ARMv7: Flush the vectors page using the base address

With the domains removal patch, the vectors page is populated using the
kernel linear mapping address. However, the flush_icache_range()
function must be called on the high vectors address because the I-cache
is allowed to have aliases (or can even be ASID-tagged VIVT). Note that
on ARMv7 processors the D-cache is non-aliasing.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: stable@vger.kernel.org
OMAP: EMIF: fix LP_MODE_PWR_DN value definition

OMAP: EMIF: fix LP_MODE_PWR_DN value definition

According to TRM the EMIF Power-down mode is identified
by value 0x4 (EMIF_PWR_MGMT_CTRL.REG_LP_MODE)

Change-Id: I4d9b9534dea27ab4619af5b6d78de8ab14f0fead
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
OMAP4: PM: fix overconsumption on OFF mode

The wrong value of CM_L3INIT_CLKSTCTRL.CLKTRCTRL = 2 (SW_WKUP)
has been stored in SAR during omap4_sar_save() execution and
causes power over consumption on OFF mode due to C2C operation.
It happens because the L3INIT CD need to be enabled during
omap4_sar_save() execution for proper USBHOST module context storing.

Problematic use case:
1) OMAP goes to sleep,
2) modem wakeup the C2C, the EMIF but the MPU is still sleeping
(as expected)
3) Modem release all his constraints, C2C is turned to OFF.
4) but OMAP never reach again OFF while we don't wakeup the CPU
(by a keypress for example), sys_clk is already ON and voltages
are not equal to 0. (OPP 50 for CORE_3 and retention voltages
for both VCORE1 and VCORE2).

As WA overwrite CM_L3INIT_CLKSTCTRL.CLKTRCTRL = 0x1 (SW_SLEEP).

Change-Id: I2e453c07f61bab28a7213dd66044fd41a021961b
Signed-off-by: Arthur Cassegrain <a-cassegrain@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>

Patch Set 1
HSMMC:Set disable timeout to 1ms

The disable timeout is reduced from 100ms to 1ms in order
to obtain aggressive power saving.

Cherry picked from p-android-omap-2.6.35 commit ID:
50df9d10a9b33c82ad02003686050b12b03d4dfe

Change-Id: Ieaa47d51396e7b92f6c1ba71e62900c58a05a26c
Signed-off-by: Madhusudhan Chikkature <madhu.cr@ti.com>
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
MMC: OMAP HSMMC: Enable Auto CMD12

Configure OMAP HSMMC module to support Auto CMD12.
This will increase throughput during multi-block
command operations as CMD12 does not have to be
explicitly sent each time by software intervention.
Instead, hardware will send CMD12 after desired
number of blocks are transferred.

Change-Id: I37bf31399c80531d9fd76baa736a59a118c769b0
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
mmc: OMAP HSMMC: Add cmd23 support

Add support for set block count, close ended transfer

Change-Id: Iab7386e1171a42ebdf55306fbf291a3e6dd85b40
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
omap4-hsmmc : Adding ADMA support

Adds ADMA support for HSMMC controllers 1 & 2 on OMAP4
Ensure dma-sg list coming from block layer is unmapped after
every transfer completion.

Change-Id: I1b898f771a3119804920c5cd17ec9c4456c60916
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
Signed-off-by: David Taylor <x0158378@ti.com>
mmc: omap: align adma and dma table entries

mmc->max_segs to core layer was set to 1024, but
adma table entry could only hold 512 entries. Increase
adma table entry size to 1024 from 512 to avoid mismatch.

Also set max_blk_count, max_req_size to what adma can
handle.

Change-Id: I8e08ee39bfa966bdf8a6c4374aea82b34fedcc62
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
mmc: omap: Increase number of blks we can handle

The above block layer is doing a "min" of max_req_size
and max_blk_count*512 before submitting each request.

As a result, the maximum size of request we are getting
is only 120*512 = 60KB even though each line in the
ADMA table can handle can handle that data alone.

So, we increase the max_blk_count we can handle. Also,
note that worst case is when above block layer gives
us 512 segments, in which there are 511 single block
entries, but one large block that is of size
mmc->max_req_size - (511*512) bytes.

In this case, we use the reserved 512 table entries
to break up the large request. Also adjust the
max_segs accordingly.

Change-Id: I733effdebea94f51a49bbf323950529afbb00dc4
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
omap-hsmmc: Implementation of i761 errata

Errata description:
Due to a bad behavior of an internal signal, the Card Error interrupt bit
MMCHS_STAT[28] CERR may not be set sometimes when an error occurred in the
card response.

Workaround:
After responses of type R1/R1b for all cards and responses of type R5/R5b/R6
for SD and SDIO cards, software must read two registers: MMCHS_RSP10 and
MMCHS_CSRE. When a MMCHS_CSRE[i] bit is set to 1, if the corresponding bit at
the same position in the response MMCHS_RSP10[i] is set to 1, the host
controller indicates a card error and software should proceed in the same way
as if a CERR interrupt would have been detected in the MMCHS_STAT register.

Note:
This errata is applicable for omap44xx.

Change-Id: Ib024bfb0624df04b7d6c61c129cbd9a34f919814
Signed-off-by: Semen Protsenko <semen.protsenko@ti.com>