ENGR00233391-1: [MX28] add new API to measure battery temperature

Add new API to measure battery temperature through LRADC

Signed-off-by: Grace Si <b18730@freescale.com>
ENGR00233391-2: [MX28] add new API to measure battery temperature

Add new API to measure battery temperature through LRADC

Signed-off-by: Grace Si <b18730@freescale.com>
ENGR00233866: SAHARA4 RNG fails to auto-seed

Problem description:
The SAHARA driver hangs when more than 8192x1024 bytes of random data
are generated.

Explanation:
When auto-seed is enabled, SAHARA generates a seed every 4094x1024bytes.
The first seed is generated when auto-seed is set during the
initialization. At the same time, a second seed is generated, and will
replace the first one when 4094x1024bytes of random data are generated.
When it reaches that required number of bytes, a third seed should be
generated in anticipation to replace the second seed.
That seed is never generated, and the status bit request for
seed is set.
The next time the number of generated bytes reaches 4094x1024, the
descriptor that requests random data cannot be processed.
The driver hangs there waiting for the descriptor to finish, and this
never occurs. A reset of SAHARA does not recover from there, and a reset
of the chip is necessary.

Tried board:
This shouldn't be related to a board, just need a chip with SAHARA4 such
i.MX51.
i.MX53 might be affected too, but I did not verify it.

Detailed reproduce steps:
(1) Replace the attached rand.c in place of the default in the imx-test
package. It requests more than 8192x1024bytes which is the limit when it
hangs. It displays the amount of generated bytes every 4096x1024bytes.
(2) Use the attached 'go' script to only run the random data test in the
unit_tests.
The test will hang.

Solution:
After discussing with STC design team, there is no evidence of an IC
bug, but there is obviously a problem.
I provided a patch that allows to disable the auto-seed, and in the
fsl_shw_get_random function, a seed is generated manually through a
descriptor every 16Mbytes. This number is higher than default auto-seed,
but was suggested by design team. There is no need to re-seed
too often.
Alternative could be to do that every XX hours, or every YY
requests to that function,

The default schedule method to wait for events has been
replaced by "wait_event_interruptible_timeout" as in case
there is problem with SAHARA, such that issue, the driver
does not hang, and can report a problem.

Signed-off-by: Terry Lv <r65388@freescale.com>
ENGR00239948: gpio_get_value() always return 0 for output gpio pins

If GDIR[n] is set and IOMUX input mode is GPIO, then the pin is
configured as GPIO output pin and the output line is driven by
writing to DR[n]. In this case, when SION bit is not set, PSR[n]
is not the same as DR[n] and reading PSR[n] will not reflect the
true value of GPIO output pin. The patch directs the
gpio_get_value() to read DR[n] when the pin is GPIO output.

Signed-off-by: Peter Chan <B18700@freescale.com>
ENGR00242159 MX5-Fix defect about cpu frequency change in DVFS

When setting the ARM_FREQ_SHIFT_DIVIDER bit in CCM_CDCR by DVFS,
it is possible that this bit remain set due to a pre-mature return
from set_cpu_freq() in dvfs_core.c. If the ARM_PODF field in
CCM_CACRR is modified at the same time by bus frequency change,
the system will run into dead loop becauae the ARM_PODF_BUSY bit
in CCM_CDHIPR will never clear indicating the ARM_PODF is always
busy.

This patch extends the mutual exclusive locking at set_cpu_freq()
in dvfs_core.c to protect the cpu frequency change by DVFS.

Signed-off-by: Peter Chan <B18700@freescale.com>
ENGR00209679-1: [MX28] When change bus frequency, randomly system hangs

Fix MX28 bus freq change issue

Signed-off-by: Grace Si <b18730@freescale.com>
ENGR00209679-2: [MX28] When change bus frequency, randomly system hangs

Fix MX28 bus freq change issue

Signed-off-by: Grace Si <b18730@freescale.com>
ENGR00234894: [MX28] - power source configuration enhancement and bug fix

1. Add battery-only configuration handling. For battery-only configuration,
   there is no 5V handoff checking, battery charging state machine will not
   start.

2. In normal boot case, 5V plug and unplug debounce checking has problem.
   Add a flag to synchronize the debounce checking start time.

Signed-off-by: Grace Si <b18730@freescale.com>
ENGR00236853-1: [MX28] - add suspend-to-ram feature

Add suspend-to-ram feature for MX28. In MX28 suspend-to-ram mode,
MX28 chip is off, only PWSITCH can resume it.  When resume,
it performs a cold boot, after bootlet runs,  it will  check the
persistent to decide whether to jump the specified DRAM address to resume.
Because it is cold boot, so all the registers values are lost and need be
restored when resume. The drivers need restore the register values when
resume from suspend-to-ram.

Signed-off-by: Grace Si <b18730@freescale.com>
ENGR00251985: ENGR00236853-02: [MX28] - add suspend-to-ram feature

Add suspend-to-ram feature for MX28. In MX28 suspend-to-ram mode,
MX28 chip is off, only PWSITCH can resume it.  When resume,
it performs a cold boot, after bootlet runs,  it will  check the
persistent to decide whether to jump the specified DRAM address to resume.
Because it is cold boot, so all the registers values are lost and need be
restored when resume. The drivers need restore the register values when
resume from suspend-to-ram.

Signed-off-by: Grace Si <b18730@freescale.com>
ENGR00240077-1: [MX28] system can't wake up from suspend with 5V only build

During suspend and resume, only normal power source case need handle battery
charging. NO_DCDC_BATT_SOURCE and NO_VDD5V_SOURCE don't need handle battery
charging.

Signed-off-by: Grace Si <b18730@freescale.com>
ENGR00240077-2: [MX28] system can't wake up from suspend with 5V only build

When enter suspend mode, ILIMIT_EQ_ZERO should not set be set.

Signed-off-by: Grace Si <b18730@freescale.com>
ENGR00239953: [MX28_EVK]Fail to reboot system with reboot command

HW_CLKCTRL_RESET_CHIP should be used in mxs reset function, it will
reset the ENTIRE chip.

Signed-off-by: Grace Si <b18730@freescale.com>
ENGR00241442 net: fix segmemtation fault caused by set port mirror

Switch:Set port mirror will cause segmemtation fault at the
first time.100%.

Run unit_test program:
./mxc_l2switch_test.out eth0 setportmirror 0 2 0 1 0
 0 0 0 12345678 2345 1

kernel dump info:
Unable to handle kernel NULL pointer dereference at virtual
address 00000030
Modules linked in:
CPU: 0    Not tainted  (2.6.35.3-662-gffedc42 #1)
PC is at switch_enet_ioctl+0xd00/0x22c0
LR is at 0x1
pc : [<c027b684>]    lr : [<00000001>]    psr: 60000013
sp : c7107d38  ip : 00000020  fp : c7107e24
r10: bed76bfc  r9 : c7106000  r8 : 00000001
r7 : 00000000  r6 : 00000000  r5 : 00000030  r4 : c8908000
r3 : 00000030  r2 : 00000000  r1 : bed76c04  r0 : 00000010
Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 0005317f  Table: 4710c000  DAC: 00000015
Process mxc_l2switch_te (pid: 2158, stack limit = 0xc7106270)
Stack: (0xc7107d38 to 0xc7108000)

Backtrace:
[<c027a984>] (switch_enet_ioctl+0x0/0x22c0) from [<c032ac90>] (dev_ifsioc+0x2b0/
0x2f0)
[<c032a9e0>] (dev_ifsioc+0x0/0x2f0) from [<c032b350>] (dev_ioctl+0x680/0x764)
r6:00009108 r5:c0562f08 r4:bed76adc r3:00000001
[<c032acd0>] (dev_ioctl+0x0/0x764) from [<c03177c4>] (sock_ioctl+0x214/0x24c)
[<c03175b0>] (sock_ioctl+0x0/0x24c) from [<c00cd914>] (vfs_ioctl+0x34/0xb4)
r6:00009108 r5:bed76adc r4:c7da5900 r3:c03175b0
[<c00cd8e0>] (vfs_ioctl+0x0/0xb4) from [<c00cdfc4>] (do_vfs_ioctl+0x528/0x590)
r6:00009108 r5:c7da5900 r4:bed76adc r3:c7a5c180
[<c00cda9c>] (do_vfs_ioctl+0x0/0x590) from [<c00ce084>] (sys_ioctl+0x58/0x7c)
r9:c7106000 r8:00000000 r7:00000003 r6:00009108 r5:bed76adc r4:c7da5900
[<c00ce02c>] (sys_ioctl+0x0/0x7c) from [<c00308c0>] (ret_fast_syscall+0x0/0x2c)
r8:c0030a68 r7:00000036 r6:bed76ec2 r5:00009108 r4:00000003
Code: e1a02008 eb04d513 e5845040 e5943040 (e5932000)

The root cause is loss pointer symbol cause non-valid pointer use.

Signed-off-by: Fugang Duan  <B38611@freescale.com>
ENGR00241779: Revert "ENGR40464722 ALSA: enable the SAIF by toggle the RUN bit"

This reverts commit af645c810892ed96a8bced86de3a15b856a6bb5d.
The toggle method could not be applied to mx28evk board, because it use
saif->mclk as mclk of external codec:sgtl5000, saif->mclk is available
only when run bit setting.

Signed-off-by: Lionel Xu <r63889@freescale.com>
ENGR00239575: mx28-usb: fixed msc cannot work after resumed from mem mode.

USB PHY cannot operate after cut off the power by mem suspend, so soft reset
and power it up when resume from mem.

Signed-off-by: Jacky Leung <b18719@freescale.com>
ENGR00252150 Fix MX53 IOMUX setup for all UARTs

The UART TXD and CTS IOMUX for all UARTs is setup incorrectly as
the code writes to the INPUT_SELECT register to configure these pins
as input. This is not needed since we are configuring the UARTs as
DCE devices. Discussion from the community can be found below:
https://community.freescale.com/thread/304402

Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan@freescale.com>