Make code/build changes to for Altera/Quartus weak notion of "library", but still working with modelsim/isim.
-- To use a "library" in quartus, you need a VHDL package file to "export" the component interfaces in the
-- library, whether the library code is vhdl or verilog (to reference the library from VHDL at least).
-- Also, since library sources cannot be precompiled in quartus (as opposed to ise/xst, modelsim, isim, ghdl)
-- for quartus, entities MUST be in their own files whose name matches the entity. So the basic VHDL files
-- have been reorganized to work with Quartus libraries, which doesn't harm how they work with the other
-- tools.
components/bias_vhdl.hdl/Makefile: suppress building vhdl workers on virtex5 and spartan3adsp
-- this is due to the vhdl code crashing the xilinx tools with no error message.
-- hopefully we'll be able to figure out how to code around the tool crashes and/or
-- get a patch (unlikely for these old parts).
components/dds_complex.test/ddsTest.cxx: centos6 new compiler warnings/errors
components/genExpected.test/genExpected.cxx: ditto
components/mixer_complex.test/mixerTest.cxx: ditto
components/delay.hdl/Makefile: remove now-unnecessary/incorrect libraries
components/unit.test/unitTest.cxx: ditto
hdl/primitives/ocpi/Makefile: major changes for the purposes stated for this update
-- Generate individual files for all data types so quartus can find them on demand.
-- Rename and break apart other files for the same purpose.
hdl/primitives/ocpi/ocpi_util_impl.vhd: use new method of instantiating verilog in a library from VHDL
-- Verilog libraries always have a eponymous package, so use it. (e.g. bsv.bsv.FIFO).
hdl/primitives/ocpi/props_pkg.cpp_vhd: new name for ocpi.props package file
hdl/primitives/ocpi/proptypes.cpp_gen: new name for file that generates all types of property entities
hdl/primitives/ocpi/util_pkg.vhd: remove redundant component declarations that are now in bsv_pkg.vhd
hdl/primitives/ocpi/wci_pkg.vhd: new name for ocpi.wci package file
hdl/primitives/util_stratix4/Makefile: rename shadowed BRAM modules so Quartus can find them properly
hdl/primitives/vendor_altera/Makefile: tag this library has having no library dependencies
jkvm6.sh: make xilinx license file explicit, not implicit, suppress opencv
jkvm_env_linux_x86_64.sh: ditto
tools/cdk/include/hdl/hdl-pre.mk: implement option to specify NO library dependencies
tools/cdk/include/hdl/isim.mk: allow libraries to have both vhdl and verilog (for _pkg in verilog libs).
tools/cdk/include/hdl/modelsim.mk: ditto
tools/cdk/include/hdl/quartus.mk: ditto, plus make the bitstream build more like the others
tools/cdk/include/hdl/xsim.mk: ditto
tools/cdk/include/hdl/xilinx.mk: make vivado and ise more alike
tools/cdk/include/hdl/xst.mk: ditto
tools/cdk/include/lib.mk: remove default libraries from here - they are in hdl-pre.mk now, smarter
tools/cdk/ocpigen/ocpigen/src/wip_HDL.cxx: make naming of property entities more consistent
hdl/primitives/bsv/bsv_pkg.vhd: a package exporting component definitions for VHDL callers to verilog
hdl/primitives/ocpi/control_decoder.vhd: new file taken from old ocpi_wci_impl.vhd
hdl/primitives/ocpi/decoder.vhd: new file taken from old ocpi_wci_impl.vhd
hdl/primitives/ocpi/property_decoder.vhd: new file taken from old ocpi_wci_impl.vhd
hdl/primitives/ocpi/readback.vhd: new file taken from old ocpi_wci_impl.vhd
hdl/primitives/ocpi/master.vhd: new file taken from old ocpi_wsi_impl.vhd
hdl/primitives/ocpi/slave.vhd: new file taken from old ocpi_wsi_impl.vhd
more thorough cleaning for platforms, and altera platform fix when building other platforms too
isim tweaks for out-of-tree library building
More out-of-tree building and altera library tweaks, plus make delay worker in sync with BSV verilog
components/specs/delay_spec.xml: force 8-bit values and byte enables to be consistent with the BSV code.
hdl/primitives/ocpi/Makefile: move util modules to their own files (used by fsk app)
primitives/ocpi/util_pkg.vhd: fix component declarations that were not used before
tools/cdk/include/hdl/hdl-assy.mk: make reference to assy core to be more universally correct
tools/cdk/include/hdl/hdl-lib2.mk: improve build messages when building workers
tools/cdk/include/hdl/hdl-pre.mk: support referring to libraries where they are built,
-- avoiding the necessity of having a separate "install" location in simple cases.
tools/cdk/include/hdl/hdl-worker.mk: cleanup some junk, improve build message.
tools/cdk/include/hdl/isim.mk: support new direct-to-built library references
tools/cdk/include/hdl/quartus.mk: ditto, and better messages
-- and when creating fake libraries insert directive to force the modules into the library being built
-- so when quartus "discovers" the module file and reads it, it goes into the right VHDL library
-- all without cluttering the actual source code