PDP8: Fix to allow character read rate to exceed the clock tick rate.  Solves issue #86
PDP8/PDP11/VAX: Support high speed character input on console and other multiplexer ports instead of limiting input data rate to 1 character per clock tick.
PDP11: Fix to correctly set PS value on CPU reset to reflect the model specific ways real hardware behaved. (from Bob Supnik)

Here's a PDP11 SIMH bug as old as the simulator itself: the reset_cpu routine sets the PS to 340 (interrupts disabled). This causes some versions of Lunar Lander not to work. In fact, the initial state of the PS is not architecturally standardized:

      04: cleared (from schematics)
      05: cleared (from manual)
      20: cleared (from schematics)
      34: cleared (from schematics), set to 340 on boot?
      40: cleared (from schematics)
      44: cleared on init, set to 340 on boot (from schematics, manual)
      45: cleared (from schematics)
      60: cleared (from schematics)
      70: cleared (from schematics)
      T11: set to 340 (from spec)
      LSI11, F11: 4 mode behavior (from memory on power recovery, cleared on GO, 340 on boot, mode 3 undefined)
      J11: 4 mode behavior (from memory on power recovery, cleared on GO, 340 on boot, 340 on jump to  custom PROM)

The story seems to be this. All non-VLSI PDP11s used TTL chips to implement the PS, either discrete flip-flops, or 4b registers, or both.
Starting with the first system, the 11/20, they were wired clear on the processor INIT signal (power-up or front panel START switch), so that all internal state started as 0. This worked fine, because START also reset the Unibus and cleared all interrupt enables. So even though the processor was as IPL = 0, no interrupts were possible. Then along came the LSI11...

The LSI11 implemented a line-time clock with NO INTERRUPT DISABLE. Thus, if IPL was left at 0 and a bootstrap routine from a slow device was started (e.g., a floppy drive), the clock would tick, and an interrupt would occur, before the bootstrap routine finished. Because no vectors were set up, the processor would crash. So the LSI11 started the practice, carried over to all later PDP11 VLSI chips, of setting the PS to 340 before jumping to a boot ROM.

The T11 did this in all modes of startup, because its only startup behavior was to jump to a "boot" routine. It did not have a console of any kind.

Accordingly, it appears that the cpu_reset routine needs to set the PS based on the processor model. Further, all boot routines need to set the PS to 0 or 340 based on the processor model. (It's probably safe for boot routines just to set the PS to 340, but it's not technically
accurate.)
PDP8: Refinement to prior fix for issue #86.  Avoid data loss if prior character hasn't been read yet when a poll event happens.
Merge branch 'master' of github.com:simh/simh
SCP/TMXR: Fix to socket writes to return 0 bytes written as an expected condition when the output socket is full (EAGAIN or EWOULDBLOCK).
VStudio: Avoid generating debug information for Visual Studio Release builds
SERIAL: For writes to serial ports, accept both EAGAIN and EWOULDBLOCK as non-error conditions for all *nix hosts
PDP11/VAX: Properly display the device interrupt BR level for Qbus and Unibus devices in SHOW IOSPACE output
SCP: Allow bare % not followed by a digit or a alpha character to be kept while substituting arguments and environment variables in simulator commands.
SCP: Fixed 'rest of line' argument substitution %*
Compiler warning cleanup
More compiler warnings
QVSS: Fix to get the VSYNC interrupts to be more reasonable.  Addresses Issue #88.  From Mike Burke

The vertical sync interrupt generated in vc_svc() was too slow for Ultrix. The driver enables interrupts and then calls DELAY(20000), which I guess is 20ms. This translates to about 10000 simulated instructions, but tmxr_poll works out at ~75000 instructions.  I've added a new unit to simulate just the vsync interrupts activating every 8000 instructions.

This approach will completely disable the ability to idle while the QVSS device is enabled.
VAX: Avoid potential VAX simulator hangs when code may poll for console input without being interrupted
QVSS: Changed prior VSYNC fix to only interrupt quickly immediately after interrupts are enabled to avoid idling issues with the prior fix.  From Matt Burke

Also fixed Qbus memory reference issues to properly generate a machine check if the QVSS device is disabled and the frame buffer is referenced.
VIDEO: When using libSDL2, make sure we use the key scan code to index the vid_key_state array.  Also, make sure we stick to getting bare key events instead of TextInput events.
QVSS/VIDEO: Fix for mouse tracking on Ultrix from Mike Burke for issue #88
PDP11: Added missing pdp11_rk boot setup from Bob Supnik
VAX: Fix for unaligned longword access to Qbus space from Matt Burke for issue #88

When the conversational boot is waiting for input it uses a BLBC instruction to read the DUART status register and test the RXR bit. This generates an unaligned longword read in Qbus I/O space (Yuk!). I realised that the code to read unaligned data in vax_mmu is broken. It attempts to read the aligned longwords that the data spans, but there was no code to convert the unaligned pa passed in to it's aligned form, thus the wrong bytes are returned and the BLBC never sees the RXR bit.