execute_alu: move immediate decoding to mor1kx_decode

for pipelines with seperate decode and execute stages
this makes the already critical path through the adder
a bit less critical
execute_alu: bypass a/b operand muxes for div operations

Divide operations on immediates are not supported,
so a small optimisation is to use the register inputs
directly instead of goiing through the operand muxes.
execute_alu: fix typo
cappuccino/ctrl: fix stepped_into_delay_slot bug

the delay_slot signal from control stage should be used,
not the one in execute stage
cappuccino/ctrl: move branch insn decoding to mor1kx_decode
(pronto)espresso: regenerate
dcache: avoid read on write to same address

Instead of enabling the RAM bypasses when a read on write happens,
avoid the situation.
This will insert a 1 clock cycle extra latency on refill hits
and write to read accesses, but that can be considered a
good trade-off considering the bypasses are resource thirsty.
icache: avoid read on write to same address

Instead of enabling the RAM bypasses when a read on write happens,
avoid the situation.
This will insert a 1 clock cycle extra latency on refill hits,
but that can be considered a good trade-off considering
the bypasses are resource thirsty.
cappuccino/fetch: remove debug printout
cappuccino/fetch: remove superflous check for ctrl_branch_exception_i

it's implied by the doing_rfe_i that ctrl_branch_exception_i is
asserted
cappuccino/lsu: register dbus_err_i in lsu instead of dcache
cappuccino/fetch: (always) register ibus_err_i
cappuccino/ctrl: remove flag write to esr

The situation the comment describes isn't valid anymore,
EPCR will never point past the l.sf but only at it,
so the work-around can be removed.
Not only is the situation not valid, the workaround will
create a bug in case of an exception happening in a delay
slot of a l.bf and the delay slot instruction is an l.sf.
The l.bf will then be rerun with the flag evaluated in the
delay slot.
execute_alu: simplify stall logic for multicycle ops