hdl/testbench/*/wb_acq_core_test/*: (5/5) add data acquisition module

Add testbenches for the acquisition module
hdl/top/pcie/bpm_pcie_ml605.vhd: comment out signals

This was necessary, in order to use an external set
of DDR3 UI signals
hdl/platform/*/Manifest.py: fix wrong pathname
hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/*: add wb_acq_core module

This commit adds the data acquisition core to the pcie design
to demonstrate DMA read/write from the SDRAM
hdl/modules/*/wb_acq_core/*: move declarations to dbe_wishbone_pkg
dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd: fix stall logic

We must only get new data from the fc interface when we are
not stalled. This is necessary due to the one cycle-long
delay between stall assertion by the fc_source modules
and the registration and preparation of the inputs
dbe_wishbone/wb_acq_core/fc_source.vhd: fix stall assertion

The assertion of the stall and dreq signals was not registered
on output. This was causing timing errors. Also, the stall signal
was being asserted one cycle before the necessary. Because of this,
modules that relied ont this behaviour must be changed.
dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd: fix stall logic

The stall FIFO reading logic was wrong as it relied on a
buggy behaviour of the fc_source module. To fix this,
it was implemented a simple first word fall through FIFO
interface and the current word is hold until the stall signal
is deasserted
hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/*: merge constraints files

The two constraints files were merge together to ease timing
analysis
hdl/top/ml_605/*/Manifest.py: update Manifest file
dbe_wishbone/wb_acq_core/acq_core_pkg.vhd: fix device id

This device ID was wrong. It was the same as a previous module.
Now it was changed to a random number
dbe_wishbone/wb_acq_core/fc_source.vhd: fix first and last data tags

Those tags were asserted combinatorially and was in the critical
path. Now, they are asserted synchronously.
hdl/top/pcie/bpm_pcie_ml605.vhd: fix missign assignment

The ref_clk was not assigned when using the module as
"INSTANTIATED". Thus, causing the ddr_core to become
unitialized forever
hdl/top/pcie/bpm_pcie_ml605.vhd: re-add RST_ACT_LOW generic

Now the user can choose whether to use an active low or high reset
hdl/modules/*/wb_acq_core/wbgen/*: remove ext_clk_i sync clock

This was causing timing errors as ext_clk_i is 2x the clk_sys
hdl/top/*/dbe_bpm_fmc130m_4ch_pcie/*: add more debug and small fixes

- Add more debug signals to chipscope
- Fix wishbone addresses
- Add slave adapter to PCIe Core
hdl/top/*/dbe_bpm_fmc130m_4ch_pcie/*: add chipscope project