Assert that the last operand is actually EFLAGS

This is another follow-up to r197503, after a post-commit review by
Andy.

<rdar://problem/15627766>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197520 91177308-0d34-0410-b5e6-96231b3b80d8
Handle i64 first for clarity. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197524 91177308-0d34-0410-b5e6-96231b3b80d8
On APCS, only try to align aggregates to 32 bits instead of 64.

This matches clang's behavior and since it is only a preference, it is not
an ABI issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197526 91177308-0d34-0410-b5e6-96231b3b80d8
MC COFF: Emit the 'b' section flag for .bss sections in GNU assembly

Without this, assembling clang's disassembly would produce an object
file with the IMAGE_SCN_CNT_INITIALIZED_DATA section characteristic
rather than the uninitialized one.  link.exe would warn when merging
comdats with different flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197529 91177308-0d34-0410-b5e6-96231b3b80d8
[DiagnosticPrinter] Use the appropriate method to print a Twine object in a
raw_ostream.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197531 91177308-0d34-0410-b5e6-96231b3b80d8
Support little-endian encodings in the FixedLenDecoderEmitter

The convention used to specify the PowerPC ISA is that bits are numbered in
reverse order (0 is the index of the high bit). To support this "little endian"
encoding convention, CodeEmitterGen will reverse the bit numberings prior to
generating the encoding tables. In order to generate a disassembler,
FixedLenDecoderEmitter needs to do the same.

This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget
(where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This
is prep work for disassembly support in the PPC backend (which is the only
in-tree user of this little-endian encoding support).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197532 91177308-0d34-0410-b5e6-96231b3b80d8
Eliminate PPC instruction decoding ambiguities

The instruction definitions in the PPC backend have a number of variants
defined for the same instruction to represent differences between 64-bit and
32-bit semantics. In order to generate a disassembler for the PPC backend, we
need to mark all but one of these as CodeGen only.

No functionality change intended; this is prep work for PPC disassembly
support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197535 91177308-0d34-0410-b5e6-96231b3b80d8
Fix N32 registers and stack alignment.

This patch fixes the "n" and "S" components of the data layout for mips. Clang
already gets this right.

This will be tested in clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197536 91177308-0d34-0410-b5e6-96231b3b80d8
DebugInfo: Introduce new DIValue, DIETypeSignature to encode references to type units via their signatures

This simplifies type unit and type unit reference creation as well as
setting the stage for inter-type hashing across type unit boundaries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197539 91177308-0d34-0410-b5e6-96231b3b80d8