git-svn-id: http://gadgetforge.gadgetfactory.net/svn/butterflylogic@314 1d4a9630-437f-4d7c-ade3-22107e79a4b7
Fix so ram writes what adv-trigger wants captured.  Minor tweaks to ensure rle-encoder & sram interface  reset to known state.


git-svn-id: http://gadgetforge.gadgetfactory.net/svn/butterflylogic@323 1d4a9630-437f-4d7c-ade3-22107e79a4b7
Removed inclusive <rle-count> mode, since breaks older clients and no longer needed by Jawi's.


git-svn-id: http://gadgetforge.gadgetfactory.net/svn/butterflylogic@324 1d4a9630-437f-4d7c-ade3-22107e79a4b7
Release 7 of Demon Core FPGA.   Fixed demux mode, issue with lost samples when first armed, cleans up rle captures when manually finished, & minor tweaks to advanced trigger.

git-svn-id: http://gadgetforge.gadgetfactory.net/svn/butterflylogic@329 1d4a9630-437f-4d7c-ade3-22107e79a4b7
Verilog source files were separated into directories, a Makefile was added
Verilog: improvised fix to a bench problem

The number of ports was not the same in the instance and RTL, the instance did not assign a value to finish_now, I used a constant 1'b0.
Verilog: some Makefile fixes
Verilog: removing Windows specific go_*.bat files
Verilog: top level module cleanup
Verilog port declaration recoded to Verilog 2001
Verilog: recoding the soon to be deprecated 'defparam' syntax
Verilog: recoded most ports to Verilog 2001, using the blocking asignment operator for FF (mostly)
Verilog: updated waveform generation code
Verilog: Makefile updates
Verilog: using nonblocking assignment operators for FF
Verilog: checked all asignment operators, fixed some regressions
Verilog: Xiling ISE synthesys tools do not support , at least not in this cotext
Verilog: removed unit delays #1 from RTL
Verilog: updated Xilinx ISE project
Verilog: SPI related changes to the testbench, RTL ports were renamed