pre-RA-sched: fix TargetOpcode usage

TargetOpcodes need to be treaded as Machine- and not ISD-Opcodes.

Signed-off-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177518 91177308-0d34-0410-b5e6-96231b3b80d8
Move SDNode order propagation to SDNodeOrdering, which also fixes a missed
case of order propagation during isel.

Thanks Owen for the suggestion!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177525 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "pre-RA-sched: fix TargetOpcode usage"

This reverts commit 06091513c283c863296f01cc7c2e86b56bb50d02.

The code is obviously wrong, but the trivial fix causes
inefficient code generation on X86. Somebody with more
knowledge of the code needs to take a look here.

Signed-off-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177529 91177308-0d34-0410-b5e6-96231b3b80d8
Annotate remaining IIC_BIN_* instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177539 91177308-0d34-0410-b5e6-96231b3b80d8
Add some missing SSE annotations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177540 91177308-0d34-0410-b5e6-96231b3b80d8
Add timing of the IR parsing code with a new -time-ir-parsing flag


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177543 91177308-0d34-0410-b5e6-96231b3b80d8
Make target-specific test case in r177474 only run when that target is built

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177545 91177308-0d34-0410-b5e6-96231b3b80d8
DIBuilder: allow linkage name to be specified for global variables

Patch by Kai Nacke (kai@redstar.de)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177547 91177308-0d34-0410-b5e6-96231b3b80d8
Remove blank line before block comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177550 91177308-0d34-0410-b5e6-96231b3b80d8
Enhance debug info namespace test to check for context/scope reference

The differing file (due to the #line directive in the original source) is for
future testing improvements coming soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177560 91177308-0d34-0410-b5e6-96231b3b80d8
Refactor file/directory path in namespace debug info to refer directly to the pair rather than the DIFile

(paired to a Clang test - excuse the buildbot skew/fallout)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177566 91177308-0d34-0410-b5e6-96231b3b80d8
Make sure TableGen exits with an error code after printing errors.

This makes it possible to report multiple errors in one invocation.
There are already calls to PrintError in CodeGenDAGPatterns.cpp which
previously would not cause TableGen to fail.

<rdar://problem/13463339>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177573 91177308-0d34-0410-b5e6-96231b3b80d8
Add std prefixes to fix the build with xlc.
Patch by Kai <kai@redstar.de>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177574 91177308-0d34-0410-b5e6-96231b3b80d8
xlC doesn't like Header being both a type and a member variable. Rename the
member variable.

Patch by Kai <kai@redstar.de>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177575 91177308-0d34-0410-b5e6-96231b3b80d8
minor code style cleanup.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177576 91177308-0d34-0410-b5e6-96231b3b80d8
Call the new llvm_gcov_init function to register the environment.

Use the new `llvm_gcov_init' function to register the writeout and flush
functions. The initialization function will also call `atexit' for some cleanups
and final writout calls. But it does this only once. This is better than
checking for the `main' function, because in a library that function may not
exist.
<rdar://problem/12439551>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177579 91177308-0d34-0410-b5e6-96231b3b80d8
Remove trailing spaces.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177584 91177308-0d34-0410-b5e6-96231b3b80d8
Correct cost model for vector shift on AVX2

- After moving logic recognizing vector shift with scalar amount from
  DAG combining into DAG lowering, we declare to customize all vector
  shifts even vector shift on AVX is legal. As a result, the cost model
  needs special tuning to identify these legal cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177586 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unused field in DICompileUnit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177590 91177308-0d34-0410-b5e6-96231b3b80d8
Annotate SSE horizontal and integer instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177591 91177308-0d34-0410-b5e6-96231b3b80d8