Compile as A15
usb: hsic: suspend hsic until really activated by the gadget driver

Hsic can enter to low power mode only after bus suspend when
connected to host. Since there is no disconnect state in hsic,
hsic remaines resumed even not activated by the gadget driver.
Therefore hsic still votes for some resources, such as clocks,
that prevent from power save modes to occur, as Vdd minimization.

This fix suspends the hsic by default, right after hsic udc driver
Initializations take place, and only on activation by the gadget
driver,aka pullup, resume the hsic device.

Change-Id: I22ecbbd66e76e28161428287e6a8b44cf42a1325
CRs-Fixed: 400263
Signed-off-by: Ido Shayevitz <idos@codeaurora.org>
msm:rq_stats: Add hotplug disable attribute

Register for suspend and resume notifications from kernel. This should
be done as part of core_initcall so as to receive notification as close
as possible to the actual event. Add hotplug_disable attribute to
rq-stats node. Set/clear this attribute based on the suspend/resume events.

CRS-fixed: 452456
Change-Id: I76fee349b57f47df40785e9c2503e2e1cc6e064e
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
msm: pm: Support for Krait Retention

Introduce a new low power state for Krait, retention.
This state will lower the voltage to the Krait core to
retention voltage in addition to clock gating. This state
will be in between WFI and Standalone power collapse in
terms of time overhead and power savings.

Change-Id: I6b1f0a0d2e4954a705a047fd4a07f4dd1fb3518a
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
(cherry picked from commit d27ca4a7526a890f9d2979acefda3561e49d2e66)

Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
(cherry picked from commit 3af7249c36ab53923fdf216df3b3ba2c7f847851)

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Seongmin Park <r_data@naver.com>
msm: pm: Adjust for events with hard wakeups

Get the next event and setup a new timer to expire
earlier than the next event after accounting for the
latency of the low power state being entered. This
will ensure that the core is active to handle the event
when it arrives.

(cherry picked from commit dc318fd0c3d04f7af9720af50c0eb0c6ed2653e9)
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>

Change-Id: I6609a886df227c68ce78e270ef7d235e07725d44
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Seongmin Park <r_data@naver.com>
msm: pm-8x60: Fix bug where device enter low power mode

An incorrect ordering in the check of allowed modes, results in
standalone power collapse not getting selected when the secondary
cores are online.

Change-Id: Idc7177b78bd0ce7563cc27afbf6c12d3bc1f9f9a
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Seongmin Park <r_data@naver.com>
msm: pm: Add support for retention on each core

Allow each core on 8974 to enter retention and retain
the state of the CPU. On 8960 as hardware restriction does
not permit all cores to enter retention at the same time,
allow only core 0 to enter retention when all other cores
are offline to maintain backward compatibility.

Change-Id: I6690e901afc9fa3a27010c264fa3acc9a0722c1a
Signed-off-by: Priyanka Mathur <pmathur@codeaurora.org>
Signed-off-by: Seongmin Park <r_data@naver.com>
msm: pm-8x60: Do not default to WFI when not enabled

Return MSM_PM_SLEEP_MODE_NOT_SELECTED in msm_pm_idle_prepare as the
default mode instead of WFI. Skip enter low power mode when this
mode is selected.

Change-Id: Id4a07ba1353b358726c81ed441e0327a9154de8a
Signed-off-by: Priyanka Mathur <pmathur@codeaurora.org>
Signed-off-by: Seongmin Park <r_data@naver.com>
msm: pm: Add API to enable/disable retention mode

On 8974 targets, retention mode voltage is controlled by the LDO
regulator, which in turn is powered through a ganged PMIC regulators. At
certain low voltage levels, the ganged PMIC will not be able to power
the LDO retention voltage. The regulator framework would invoke this
API to enable/disable retention mode in these scenarios.

When disabling retention modes, send a IPI to wakeup all online cores
out of idle, to ensure that no core is in a retention low power mode.
Also, disabled support for retention during suspend/hotplug operations
to ensure that a CPU isn't already in retention when the voltage is
lowered. This shouldn't have an effect on suspend, as the driver always
chooses the deepest sleep mode for suspend/hotplug.

Change-Id: I0af18168968c2aaf05ca99188d30762612c87de6
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/no-pm.c
	arch/arm/mach-msm/pm-8x60.c
	arch/arm/mach-msm/pm.h

Signed-off-by: Seongmin Park <r_data@naver.com>
msm: tracing: Add ftrace support for LPM driver

Add trace event support to capture various parameters
of low power modes like power collapse, standalone power
collapse, retention and wfi during its entry and exit.

Change-Id: I0f8b918702ae47b354aa193aa7ef20b48110fb0f
Signed-off-by: Priyanka Mathur <pmathur@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/pm-8x60.c

Signed-off-by: Seongmin Park <r_data@naver.com>
msm: pm-8x60: Merge msm_pm_idle_prepare into msm_pm_idle_enter

Modify LPM drivers to call msm_pm_idle_enter when idle. enter_sleep will
look at available time to sleep and the latencies of different low power
modes and decide the low power mode to enter. It returns the low power
mode enumeration back to cpuidle.

Change-Id: Ide88761aa2954b7d4129b1f5c497374773679012
Signed-off-by: Priyanka Mathur <pmathur@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/cpuidle.c
	arch/arm/mach-msm/no-pm.c
	arch/arm/mach-msm/pm-8x60.c

Signed-off-by: Seongmin Park <r_data@naver.com>
msm: pm-8x60: Don't save or restore GIC,VFP state in power collapse

Don't save or restore the GIC,VFP registers when entering or exiting power
collapse. The GIC and VFP drivers already register for PM notifications and
do the respective save/restore thereby making these operations redundant in
pm-8x60 driver.

Change-Id: If9969f8052843b2c7c1417dfeceaab203c6453b5
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/pm-8x60.c

Signed-off-by: Seongmin Park <r_data@naver.com>
msm: pm-8x60: Add early return to msm_pm_enable_retention()

If retention is already disabled, it is not necessary to send IPIs to
the running CPUs to wake them up. Insert an early return for this
scenario to reduce overhead during Krait rail voltage scaling, which
calls this API on every voltage change.

Change-Id: I5db0bafae187ff8a68488e86d4787df9c45787e4
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Signed-off-by: Seongmin Park <r_data@naver.com>
msm: event_timer: Support to add event timers.

Add support to allow drivers to specify future events
that need to be treated as hard deadlines. Upon event timer
expiry the driver will be notified by callback function
that the driver provides.
The pm code can query the earliest event and modify
the event timer accounting for the back off based on the
latency of the low power mode being entered.

Change-Id: Iec26f77de3b826bff456b12f3230268d9bdc2255
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Signed-off-by: Seongmin Park <r_data@naver.com>
msm: event_timer: Fix potential race condition

There is a possible race condition which could happen in the following
scenario:

Core 0 PC: lock_hrtimer_base

 lock_hrtimer_base
 hrtimer_get_remaining
 get_next_event_time
 msm_pm_idle_prepare
 msm_cpuidle_enter

Core 1 PC: generic_exec_single

 generic_exec_single
 smp_call_function_single
 setup_event_timer
 mdp_update_pm

If core0 idle thread runs before core1 has had the chance to make the
smp_call_function_single, then idle thread could end up spinning on
lock_hrtimer_base() since setup_event_timer adds an event to the event
queue but the smp cross call is the one that initializes the event timer.
So Core0 could spin on lock_hrtimer_base() since CPU1's SMP call won't be
handled as idle thread runs in noirq context.

To prevent this scenario make a change to the code flow to do the queue
operations and the timer operations on the same CPU. Meaning
setup_event_timer will only make an SMP cross call to re-organize the event
queue and reset the event timer all of which will be run on CPU0.

CRs-fixed: 425587
Change-Id: I53fc551d18f350c47e05a94976b56a5fd2e9050b
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Signed-off-by: Seongmin Park <r_data@naver.com>
msm: tracing: Add ftrace support for LPM resources

Add trace event support to capture sleep value for
each of the lpm resources l2, pxo, vdd mem and vdd
dig during power collapse.

Change-Id: Ie0d7528ecd5a87631ff584953bfe0bd77043add9
Signed-off-by: Priyanka Mathur <pmathur@codeaurora.org>
Signed-off-by: Seongmin Park <r_data@naver.com>
msm: tracing: Fix path error

Signed-off-by: Seongmin Park <r_data@naver.com>
event_timer: Add spinlock protection to event time update

Modify call flow to allow only one thread to make the smp cross call in
order to setup the event timer. Added more concurrency protections.
This helps fix a kernel data abort , where the stack looks like

Unable to handle kernel NULL pointer dereference at virtual address 0000008
pgd = d833c000
[00000008] *pgd=00000000
Internal error: Oops: 5 [#1] PREEMPT SMP ARM
Modules linked in: mwlan_aarp(PO)
CPU: 0    Tainted: P        W  O  (3.4.0-perf-gf36610b-dirty #3)
PC is at __rb_rotate_left+0xc/0x70
LR is at rb_insert_color+0x100/0x12c
pc : <c02400e8>    lr : <c02402c0>    psr: 00000093
sp : d7b4db58  ip : 00000000  fp : 400bf518
r10: c0e957b8  r9 : 0000047c  r8 : 00000000
r7 : c0dcc1fc  r6 : d8ed9900  r5 : d8ed9900  r4 : d8f55ac0
r3 : 00000000  r2 : d8f55ac0  r1 : c0dcc1fc  r0 : d8ed9900
Flags: nzcv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 10c5787d  Table: 98d3c06a  DAC: 00000015

(__rb_rotate_left+0xc/0x70) from (rb_insert_color+0x100/0x12c)
(rb_insert_color+0x100/0x12c) from (timerqueue_add+0x8c/0xbc)
(timerqueue_add+0x8c/0xbc) from (create_timer_smp+0x58/0xb8)
(create_timer_smp+0x58/0xb8) from (smp_call_function_single+0xc8/0x1c8)
(smp_call_function_single+0xc8/0x1c8) (mdp_update_pm+0xa4/0xb0)

The kernel data abort was likely due to a double add meaning adding the
same node twice, serializing the smp cross call should help this issue.

CRs-fixed: 442891
Change-Id: I572550b75ca18cdccc474103d863e8a924bccbba
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Signed-off-by: Seongmin Park <r_data@naver.com>
sched: Create sched_select_non_idle_cpu() to give preferred CPU for power saving

In order to save power, it would be useful to schedule light weight work on cpus
that aren't IDLE instead of waking up an IDLE one.

By idle cpu (from scheduler's perspective) we mean:
- Current task is idle task
- nr_running == 0
- wake_list is empty

This is already implemented for timers as get_nohz_timer_target(). We can figure
out few more users of this feature, like workqueues.

This patch converts get_nohz_timer_target() into a generic API
sched_select_non_idle_cpu() so that other frameworks (like workqueue) can also
use it.

This routine returns the cpu which is non-idle. If the local CPU isn't idle OR
all cpus are idle, local cpu is returned back. If local cpu is idle, then we
must look for another CPU which isn't idle.

This patch reuses the code from get_nohz_timer_target() routine, which had
similar implementation.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Seongmin Park <r_data@naver.com>
timer: hrtimer: Don't check idle_cpu() before calling get_nohz_timer_target()

Check for current cpu's idleness is already done in implementation of
sched_select_non_idle_cpu() which is called by get_nohz_timer_target(). So, no
need to call idle_cpu() twice, once from sched_select_non_idle_cpu() and once
from timer and hrtimer before calling get_nohz_timer_target().

This patch removes calls to idle_cpu() from timer and hrtimer.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Seongmin Park <r_data@naver.com>