Started to fix issues with the SPI driver.
Minor.
Semi functional SPI bus. Many issues fixed. However, there is this strange thing were the MSB of the ADC data is always 1 for some reason.
Fixed MISO MSB read issue. However, there is still a problem where the mirrored DAC cannot output values around zero. Not sure if this this is happening on read or write.
Fixed the SPI lines completely. It was a timing issue - not enough time from falling edge of clock to MOSI out.
full loop time characterized; jitter is around 4us
ready, set, go. added io config at c-level
implemented (but not tested) multi channel dac
minor syntax changes
adding memory commenting
updated ddr memory offset to allow for maximum cycle numbers before resetting
setup prushared+ddr communication for config register. now includes ai, ao, and frequency
cleaning up