Add support for an alternative encoding of 'PUSH reg', viz FF /6,
that is used by MSVC generated code.  Fixes #324834.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2786 8f6e269a-dfd6-0310-a8e1-e2731360e62c
amd64 front end: accept XACQUIRE and XRELEASE on exactly the insns that
the Intel docs say can validly have them.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2787 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Tidyup -- no functional change.  Replace all "pfx & PFX_LOCK"
with haveLOCK(pfx).


git-svn-id: svn://svn.valgrind.org/vex/trunk@2788 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Power 8 support, phase 5 

This commit adds support for the following instructions for doing
various arithmetic, bit transformation, cipher, count, logical,
and SHA operations.

  vpmsumb, vpmsumh, vpmsumw, vpmsumd, vpermxor, vcipher, vcipherlast,
  vncipher, vncipherlast, vsbox,
  vclzb, vclzw, vclzh, vclzd,
  vpopcntb, vpopcnth, vpopcntw, vpopcntd,
  vnand, vorc, veqv,
  vshasigmaw, vshasigmad,
  bcdadd, bcdsub

The following Iops were added to support the above instructions:
  Iop_BCDAdd, Iop_BCDSub, 
  Iop_PolynomialMulAdd8x16, Iop_PolynomialMulAdd16x8,
  Iop_PolynomialMulAdd32x4, Iop_PolynomialMulAdd64x2,
  Iop_CipherV128, Iop_CipherLV128, Iop_CipherSV128,
  Iop_NCipherV128, Iop_NCipherLV128,
  Iop_SHA512, Iop_SHA256, Iop_Clz64x2

The patch is for Bugzilla 325628


git-svn-id: svn://svn.valgrind.org/vex/trunk@2789 8f6e269a-dfd6-0310-a8e1-e2731360e62c