target-arm: A64: add support for logical (immediate) insns

this patch adds support for C3.4.4 Logical (immediate),
which include AND, ANDS, ORR, EOR.
It also includes a way to access the registers when
register 31 means SP.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder, function renaming,
          removed a TCG temp variable]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
target-arm: A64: add preliminary support for MSR/MRS

this is very very limited: we only support
setting and getting NZCV (C4.3.10),
getting CTR_EL0 (D8.2.21) with a hardcoded value,
getting DCZID_EL0 (D8.2.23) with a hardcoded value,
getting and setting TPIDR_EL0 (D8.2.87).

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder structure, put common code
          between MSR/MRS in a separate function, add NZCV,
          add support for writing to TPIDR_EL0,
          fixed high bit of CTR_EL0]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
target-arm: A64: MRS/MSR for FPCR and FPSR access

Add FPCR and FPSR to the set of registers handled by MRS/MSR;
implemented via calls to helper functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>