- Adding harmonica.cpp and Makefile for reference. Very minor changes were made and it is suggested to use the harmonica version from harmonica's git. Just merger some of these changes with them mainly involving ifdef statements and flags for SIMD/Cache support.
- Adding snapshots of DDR2 megacore configuration used for reference.
- Adding a new de3 display module which displays the 32bit performance numbers on the two 7-seg displays by displaying one hex bit  and its position in the hex format one by one.
Cache bug fixes:
- Fixing the case when there is read(tag1,index1),write(tag2,index1), write(tag1,index1). Then earlier when the tag2 write-miss request is sent to memory and the tag1 write request comes in then that will be a hit and that data would be overwritten when data for tag2 returns. This is a problem even if tag2 request not sent to L2 when tag1 write comes in.
- Fixing bug which caused problem when L1 does dirty writeback and find L2 to be in stall state. Earlier it was just ignoring L2 stalls for this case and none of our apps casued this situation, so we never caught it.
- Increasing latency of mem_dummy and making it close to the delays from DDR2. A lot of new problems are uncovered when we use high value of delay for mem dummy.
- Fixed hit logic in both L1,L2. Earlier as it only checked for tag match for the address. As tag was mostly zero, so for all our addresses, hit is asserted in the first half of clkby2 . This casued issues for some cases when we used higher addresses with different tags and same index.
- Fixed bug so that when data from L2 arrives it is served in 1 extra cycle max, so it does not gets overwritten by new data from L2. To handle this case, we changed FSM by adding logic so that when data from L2 returns and we are in READ_NEXT state then we handle it before going to READ_WAIT state. This is to handle case when data from L2 comes when we are in read-next and then again comes in WB_L2_WAIT, in WB_L2_WAIT if it comes then that will overwrite previous pending l2 returned data. (also had to made some changes in the addr_b and tag_b_valid_in signals in L1 and L2!)
- small bug fix in lsu
- minor cleaning of cache_subsystem, cache_shared