Merge pull request #2 from larsclausen/master

migen patches
fhdl/structure: binary constant builder
bank/csrgen: use enumerate
bank: refactoring
bank: support registers larger than the bus word width
bank: event manager
fhdl: do not attempt slicing non-array signals to keep Verilog happy
bus/wishbone2csr: truncate WB data
doc: update Bank description
bus: ASMI hub (untested)
bus/asmibus: add get_slots, fix get_fragment
corelogic/misc: contiguous split
corelogic/record: add to_signal convenience function
bus/asmibus: fix typo
corelogic/misc/multimux: less confusing variable name
corelogic/misc: displacer + chooser
bus: Wishbone to ASMI caching bridge (untested)
bus/wishbone2asmi: set WM, and send 0 when inactive
doc: update ASMI description
bus/csr: Rename a->adr d->dat to be consistent with the other buses