[OMAP5432][OPP] fix OPP detection

OMAP5432 SW release uses different DPLL settings than OMAP5430 release,
causing some DPLL output clock rates to be slightly different.
Fix it by using specific rates for each device.

Signed-off-by: Patrick Titiano <p-titiano@ti.com>
[OMAP5432] fix L3-derived expected clock rates

CORE DPLL settings for L3 (DDR3) clock and derived clocks is slightly different than OMAP5430 ones.
Handle it.

Signed-off-by: Patrick Titiano <p-titiano@ti.com>
[OMAP5432][DPLL] update OMAP5432 DPLL CORE OPP_NOM golden settings

Golden settings for OMAP5432ES2.0 DPLL CORE OPP_NOM are different than OMAP5430 ES2.0 ones.
Update golden settings tables accordingly.
Also handle variable DPLL CORE H14 settings (depending on GPU freq / VDD_MM OPP).

Signed-off-by: Patrick Titiano <p-titiano@ti.com>
[OMAP5432][AUDIT][DPLL][CLKSPEED] DPLL ABE running from 19.2M clock instead of 32K

DPLL cascading is no more supported.
OMAP5432ES2.0 as integrated on panda5board does not source DPLL ABE clock from 32K but 19.2M.
Update DPLL ABE golden settings accordingly, as well as AESS and L4_ABE_INTERCONNECT expected clock rates.

Signed-off-by: Patrick Titiano <p-titiano@ti.com>
update changelog and revision to v1.66

Signed-off-by: Patrick Titiano <p-titiano@ti.com>