wb_intercon: Rename sdt to rdt in wb_arbiter
wb_intercon: Rewrite wb_mux to avoid placing select logic outside of module

wb_mux previously used a slave_sel_i input and required that the slave
select logic was placed outside the module.
This is changed so that the parameters MATCH_ADDR and MATCH_MASK are used
to select slaves instead. Updates to the test bench are in this commit too
wb_intercon: Replace internal wb_master with wb_bfm_transactor
or1200-generic: Adapt to changes in wb_intercon
or1200-generic: Add UART simulation model
Add core mt48lc16m16a2
initial WIP for sockit system
sockit/rom: do endless loop instead of jump to 0x100
sockit: add internal SRAM
clkgen: remove sdram clock signals
clkgen: remove pll files and instantiate pll directly in clkgen.v
orpsoc_top: remove sdram clock and reset
orpsoc_top: remove intgen address decoding
remove olofk bug comment
pinmap: make section comments "block comments"
orpsoc_top: increase internal SRAM to 64KB
orpsoc_top: module declaration signals lineup
remove uart pad signals

There are no pins on the board to hook up an uart,
so we'll just connect them inside the fpga.
format fix
sockit: add qsys generated hps (hard processor system)