usb: hsic: suspend hsic until really activated by the gadget driver

Hsic can enter to low power mode only after bus suspend when
connected to host. Since there is no disconnect state in hsic,
hsic remaines resumed even not activated by the gadget driver.
Therefore hsic still votes for some resources, such as clocks,
that prevent from power save modes to occur, as Vdd minimization.

This fix suspends the hsic by default, right after hsic udc driver
Initializations take place, and only on activation by the gadget
driver,aka pullup, resume the hsic device.

Change-Id: I22ecbbd66e76e28161428287e6a8b44cf42a1325
CRs-Fixed: 400263
Signed-off-by: Ido Shayevitz <idos@codeaurora.org>
msm: rotator: Add proper checks for enabling Fast YUV

For rotator version 2.0 and above, there is support for fast
YUV which gives better rotator performance. However, there are
few constraints related to height under which fast YUV cannot be
enabled when 90 degree rotation is enabled. Make sure
to add proper checks before enabling fast YUV.

Change-Id: Iafd204a6e4ef09e1151d01d8fde35359b7c3b7a5
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
msm: kgsl: Allocate space in ringbuffer for EOF commands

When userspace passes end of frame (EOF) flag, ringbuffer is
inserted with EOF marker commands. Allocate ringbuffer space
for EOF marker commands.

CRs-Fixed: 469807
Change-Id: I7de8d1b81d358a8d8753ac84fbdceddad27bb17d
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
apexq: enable CONFIG_NETFILTER_XT_TARGET_TCPMSS
msm: vidc: cache-invalidate encoder output buffers after alloc

Invalidate output buffers explcitly once, during registration.
This ensures any pending CPU writes (eg. memset 0 after allocation)
are not flushed _after_the hardware has written bitstream.

b/ 11149679

Change-Id: I958466011e7d96c7b5e2691403c8386309997429
Signed-off-by: Praveen Chavan <pchavan@codeaurora.org>
msm: kgsl: Add separate GPU shader memory mapping

Add separate kernel memory mapping for GPU shader memory.
Previously, both the register and the shader memory were mapped
as one entity, with the mapping length being equal to combined
size of register memory and shader memory. Now, we separate the
shader memory mapping to help in cases of GPU devices where the
shader and register memory may not be adjacent. This helps to
dump the shader memory in the postmortem snapshot. By having a
separate mapping for shader memory, the snapshot dump routine
simply reads in the shader memory range specified and dumps.

Signed-off-by: Harsh Vardhan Dwivedi <hdwivedi@codeaurora.org>

Conflicts:
	drivers/gpu/msm/adreno_a3xx_snapshot.c

Change-Id: Ia51cdbc6a682abe6505bcc53c997ef9c9192f9e6
msm: kgsl: Add intermediate power levels

Make use of the two independent power domains to
add intermediate levels.  Attempt to just increase
the bus frequency before also raising the GPU
frequency.

Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>

Conflicts:
	arch/arm/boot/dts/msm8974-gpu.dtsi
	arch/arm/boot/dts/msm8974-v2.dtsi
	drivers/gpu/msm/kgsl_pwrctrl.c
	drivers/gpu/msm/kgsl_pwrctrl.h

Change-Id: Ibe85d1c02941430c5da83a75a09d5bc0ec5f8ec0
msm: Fix mem leak when using per-process pages

When GPU is using per process page tables the code creates
a new page table (domain) for every process. There is also
some associated structures allocated to keep track of each
domain. However, when cleaning up the memory used for a page
table only the domain is freed and not the associated structures.

Add a function to allow a client to properly unregister a domain
which will free all the memory associated with a domain.
Call the unregister function from kgsl driver code.

CRs-fixed: 480801
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/iommu_domains.c

Change-Id: I78365cac8afb900450b512527f0cb71da5e9ddb2
ARM: Add support for 64 bit register reads/writes

Add macros to read and write to 64 bit registers.

Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>

Conflicts:
	arch/arm/include/asm/io.h

Change-Id: Ied2b38e6a3803377cd271fe7b13f6cf0fc586e70
driver core: Add iommu_group tracking to struct device

IOMMU groups allow IOMMU drivers to represent DMA visibility
and isolation of devices.  Multiple devices may be grouped
together for the purposes of DMA.  Placing a pointer on
struct device enable easy access for things like streaming
DMA programming and drivers like VFIO.

Change-Id: I0a92a94aea0ac699676914a033477243a70dd0b0
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Revert "M2: ion: using client->heap_mask instead of ion_full_heap_mask in COMPAT ioctl"

This reverts commit 93891eeea2aa2d70727e2c236a0c83ebfdb63886.