changes for usb2 OUT transfers into endpoint 2
Daisho USB Core README
module updates for gig-e
gig-e updates
Moved PHY_MODEx pins from configuration to power symbol.
Removed excess libraries from schematics.
Considerable rework of DDR2 routing.
Unwired USB1 interface, since it will eventually turn into USB0 and move to the other side of the FPGA.
Added some amount of USB configuration circuitry.
Updated netlist and component mapping.
Undid USB 3.0 routing.
Preliminary DDR2 routing, testing for continuity and pin-swapping opportunities. Still a bunch of non-DQ/DQS signals need to be placed and routed.
Merge branch 'master' of github.com:mossmann/daisho