verif/dc_ram: force ram type for synthesis.

We really want this to be a ram - it's used for clock domain crossing.
rtl: fix up FPGA synthesis warnings.

Inferred latches and unused variables.
fpga: update configuration to include all source.
verif: fixup implicit wire typo.
rtl: convert bus addressing to word addresses.

There's no point in having byte addressed busses when we have the byte
enables.  Save a few bits.
sdram: udpate submodule.
sim: don't error out on read/write fails.

These will soon be converted to exceptions.
tests: fixup CMake template for multiple tests.
rtl/soc: add a default address handler.

Accessing an invalid address shouldn't result in the CPU hanging - add a
default handler that just signals an error which will later be used to
implement a data abort.