X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171064 91177308-0d34-0410-b5e6-96231b3b80d8
Harden test so it's not affected by changes to compare lowering.

This only failed on hosts that don't have SSE41.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171066 91177308-0d34-0410-b5e6-96231b3b80d8
[msan] Fix handling of select with vector condition.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171069 91177308-0d34-0410-b5e6-96231b3b80d8
[msan] Fix handling of vectors of pointers.

VectorType::getInteger() can not be used with them, because pointer size
depends on the target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171070 91177308-0d34-0410-b5e6-96231b3b80d8
Expand PPC64 atomic load and store

Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171072 91177308-0d34-0410-b5e6-96231b3b80d8
Loosen scheduling restrictions on the PPC dcbt intrinsic

As with the prefetch intrinsic to which it maps, simply have dcbt
marked as reading from and writing to its arguments instead of having
unmodeled side effects. While this might cause unwanted code motion
(because aliasing checks don't really capture cache-line sharing),
it is more important that prefetches in unrolled loops don't block
the scheduler from rearranging the unrolled loop body.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171073 91177308-0d34-0410-b5e6-96231b3b80d8
BBVectorize: Enable vectorization of the fmuladd intrinsic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171075 91177308-0d34-0410-b5e6-96231b3b80d8
LoopVectorize: Enable vectorization of the fmuladd intrinsic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171076 91177308-0d34-0410-b5e6-96231b3b80d8
Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171078 91177308-0d34-0410-b5e6-96231b3b80d8
BBVectorize: Use VTTI to compute costs for intrinsics vectorization

For the time being this includes only some dummy test cases. Once the
generic implementation of the intrinsics cost function does something other
than assuming scalarization in all cases, or some target specializes the
interface, some real test cases can be added.

Also, for consistency, I changed the type of IID from unsigned to Intrinsic::ID
in a few other places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171079 91177308-0d34-0410-b5e6-96231b3b80d8
Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171080 91177308-0d34-0410-b5e6-96231b3b80d8
Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171081 91177308-0d34-0410-b5e6-96231b3b80d8
Remove alignment from a bunch more VEX encoded operations in the folding tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171082 91177308-0d34-0410-b5e6-96231b3b80d8
llvm/test/CodeGen/X86: Disable avx in two tests corresponding to r171082.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171083 91177308-0d34-0410-b5e6-96231b3b80d8
llvm/test/CodeGen/X86: FileCheck-ize two tests in r171083.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171084 91177308-0d34-0410-b5e6-96231b3b80d8
Mark VANDNPD/VANDNPDS as not commutable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171085 91177308-0d34-0410-b5e6-96231b3b80d8
Merge an AVX/SSE 256-bit and 128-bit multiclass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171086 91177308-0d34-0410-b5e6-96231b3b80d8
Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171087 91177308-0d34-0410-b5e6-96231b3b80d8
white space

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171090 91177308-0d34-0410-b5e6-96231b3b80d8
Reformat the docs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171091 91177308-0d34-0410-b5e6-96231b3b80d8