target-arm: aarch64: expand decoding skeleton for system ins

this change splits the system instructions into
hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL,
sync instructions, which include CLREX, DSB, DMB, ISB,
msr_i, which move immediate to processor state field,
sys, which include all SYS and SYSL instructions,
msr, which move from a gp register to a system register,
mrs, which move from a system register to a gp register.

This is only the skeleton, not the actual implementation
for all the instructions above.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
target-arm: aarch64: add set_pc cpu method

When executing translation blocks we need to be able to recover
our program counter. Add a method to set it for AArch64 CPUs.
This covers user-mode, but for system mode emulation we will
need to check if the CPU is in an AArch32 execution state.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

from Alexander Graf <agraf@suse.de> aarch64 series 06/60
target-arm: aarch64: add support for B and BL insns

This adds handling for the B and BL instructions,
which require to be able to access a register and generate jumps.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: renamed functions,
          protected new A64 tcg constants in DisasContext with
          #ifdef TARGET_AARCH64,
          adapted to new decoder layout]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

from Alexander Graf <agraf@suse.de> aarch64 series 09/60
target-arm: aarch64: add support for BR, BLR and RET insns

Implement BR, BLR and RET. This is all of the 'unconditional
branch (register)' instruction category except for ERET
and DPRS (which are system mode only).

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: reimplemented on top of new decoder structure]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

from Alexander Graf <agraf@suse.de> aarch64 series 10/60
target-arm: aarch64: add support for logical (shifted register)

this adds support for the instructions described in:
C3.5.10 Logical (shifted register)

Support includes a reworking of flags, and a way to read the
registers in copy mode that also zero extends on 32bit access.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

from Alexander Graf <agraf@suse.de> aarch64 series 14/60
target-arm: aarch64: add support for ADR and ADRP

this adds support for the instructions described in:
C3.4.6 PC-rel. addressing (ADR and ADRP).

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder structure]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

from Alexander Graf <agraf@suse.de> aarch64 series 26/60