created cached instruction memory

A cached instruction memory module (im_cached) has
been created that caches values of the slow instruction
memory (im_slow).  The design is trivial at the moment.
It is just a 4-block direct mapped cached with one
word (32-bit) blocks.
internally forwarded cached data, shortened by 1 cycle

Previously the data ready in memory and on the next
cycle it would become hit.  Now when it becomes ready
it simultaneously becomes a hit, shorting the time
to access by one cycle.