PPC: Enable aggressive anti-dependency breaking

Aggressive anti-dependency breaking is enabled by default for all PPC cores.
This provides a general speedup on the P7 and other platforms (among other
factors, the instruction group formation for the non-embedded PPC cores is done
during post-RA scheduling). In order to do this safely, the incompatibility
between uses of the MFOCRF instruction and anti-dependency breaking are
resolved by marking MFOCRF with hasExtraSrcRegAllocReq. As noted in the removed
FIXME, the problem was that MFOCRF's output is sensitive to the identify of the
source register, and always paired with a shift to undo this effect. Because
anti-dependency breaking is unaware of this hidden dependency of the shift
amount on the source register of the MFOCRF instruction, changing that register
must be inhibited.

Two test cases were adjusted: The SjLj test was made more insensitive to
register choices and scheduling; the saveCR test disabled anti-dependency
breaking because part of what it is testing is proper register reuse.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190587 91177308-0d34-0410-b5e6-96231b3b80d8
Fixup for r190409: add dep on LZMA only if CMake is cross-compiling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190591 91177308-0d34-0410-b5e6-96231b3b80d8
AVX-512: implemented extractelement with variable index.
Added parsing of mask register and "zeroing" semantic, like {%k1} {z}.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190595 91177308-0d34-0410-b5e6-96231b3b80d8
Add an instruction deprecation feature to TableGen.

The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.

The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
  ComplexDeprecationPredicate<"MCR">

would mean you would have to define the following function:
  bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
                             std::string &Info)

Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.

The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
LLVM Interpreter: implementation of "insertvalue" and "extractvalue";
undef constatnt for structure and test for these functions.

done by Yuri Veselov (mailto:Yuri.Veselov@intel.com)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190599 91177308-0d34-0410-b5e6-96231b3b80d8
LLVM interpreter: added a test for insert- extract- value


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190600 91177308-0d34-0410-b5e6-96231b3b80d8
[LTO] Fix the LTO tool, after my API breakage.

Thanks to Zonr Chang!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190602 91177308-0d34-0410-b5e6-96231b3b80d8
Somehow this important part of the patch, where I actually check the Mask,
got lost during my iterations of review.

Thanks to Hal for spotting it!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190604 91177308-0d34-0410-b5e6-96231b3b80d8
Mark PPC MFTB and DST (and friends) as deprecated

Use the new instruction deprecation feature to mark mftb (now replaced with
mfspr) and dst (along with the other Altivec cache control instructions) as
deprecated when targeting cores supporting at least ISA v2.03.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190605 91177308-0d34-0410-b5e6-96231b3b80d8
Partial support for Intel SHA Extensions (sha1rnds4)

Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.

Support for the remaining instructions will follow in a separate patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8