ARC: Add missing register names for invisible registers

Registers R61 (reserved) and R62 (limm) are not accessible via JTAG, but they
must be defined and sent to the GDB. arc_gdb_reg_names_list was missing names
for those registers, but still were counted in the ARC32_NUM_GDB_REGS and hold
sites in the arrays of register values user to save/restore context, though
values on those sites were never accessed.

Signed-off-by: Anton Kolesov <akolesov@synopsys.com>
Merge pull request #8 from anthony-kolesov/add-missing-registers

ARC: Add missing register names for invisible registers
ARC: Optimize bulk operations on AUX registers

When saving/restoring context auxiliary registers are not sequential so
addresses have to be set explicitly. However still there are some register
that are sequential and this patch exploits the possibility to avoid setting
those address when it is not required. This reduces time required to
write/read auxiliary registers in bulk by about 200 ms.

Signed-off-by: Anton Kolesov <akolesov@synopsys.com>
Merge pull request #9 from anthony-kolesov/optimize-register-operations

ARC: Optimize bulk operations on AUX registers
ARC: Add partial support for Digilent HS-2 cable

Digilent HS-2 uses different chip in comparison to HS-1, FTDI 232H instead
of 2232C and it has different USB ProductID. This patch adds corresponding
PID to the ML-509 targets.

Signed-off-by: Anton Kolesov <akolesov@synopsys.com>
ARC: Refer to CPU by name instead of id

OpenOCD was printing warning that CPU should be referred by name instead of
number. This patch corrects it.

Signed-off-by: Anton Kolesov <akolesov@synopsys.com>
Merge pull request #10 from anthony-kolesov/add-digilenths2-partially

Add digilenths2 partially
Document that Digilent HS2 is not supported
ARC: Mention EM Starter Kit in readme file

Expand mentions of EM Starter Kit in readme file, so it would be clear that
it is supported.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
ARC: Fix support for big endian memory model

OpenOCD wasn't working properly with big-endian cores: operations on bytes
and half-words were done at wrong addresses, word-operations were correct.
In case of reading problem was happening because half-word or byte was
extracted from word-aligned array when it was in host-endianness, then
half-words were converted to target order. However to work instead of words
should be converted to target endianness first, then desired bytes should be
extracted. What was happening was that order of bytes in half-words was
correct, but half-word was itself wrong. Bytes also were took from invalid
address.

Another problem with existing code was that it implemented unaligned memory
access. This is not required, because generic code in OpenOCD can split
unaligned memory access to a series of aligned access. Code in arc_mem.c
worked only for little-endian host and target (maybe for big-endian host and
target as well), but not for little-endian host and big-endian target.
Considering that it is not needed and makes code only more complex I've
removed support for unaligned memory accesses in both writes and reads.
OpenOCD generic code splits memory access in a right way for both
little- and big-endian.

Signed-off-by: Anton Kolesov <anton.kolesov@synopsys.com>