target-arm: aarch64: add preliminary support for MSR/MRS

this is very very limited: we only support
setting and getting NZCV (C4.3.10),
getting CTR_EL0 (D8.2.21) with a hardcoded value,
getting DCZID_EL0 (D8.2.23) with a hardcoded value,
getting and setting TPIDR_EL0 (D8.2.87).

Eventually this could be rewritten on top of arm_cp_regs API
with some refactoring necessary (main issue: ARM_CP_64BIT)

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder structure, put common code
          between MSR/MRS in a separate function, add NZCV,
          add support for writing to TPIDR_EL0,
          fixed high bit of CTR_EL0]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

from Alexander Graf <agraf@suse.de> aarch64 series 35/60, 36/60
target-arm: aarch64: add support for conditional branches

This patch adds emulation for the conditional branch (b.cond) instruction.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder structure,
          reused arm infrastructure for checking the flags]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 34/60
target-arm: aarch64: add support for conditional select

this patch adds support for "C3.5.6 Conditional select",
which means CSEL, CSINC, CSINV, CSNEG.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 43/60
target-arm: aarch64: add support for 'test and branch' imm

this patch adds emulation for the test and branch insns,
TBZ and TBNZ.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted for new decoder,
          always compare with 0, remove a TCG temporary]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 40/60
target-arm: aarch64: add support for compare and branch imm

this patch adds emulation for the compare and branch insns,
CBZ and CBNZ.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder,
          compare with immediate 0, use read_cpu_reg to get
          the 0 extension on (!sf)]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 33/60
target-arm: aarch64: add support for EXTR

This patch adds emulation support for the EXTR instruction.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted for new decoder, removed a few temporaries,
          fixed the 32bit bug, added checks for more
          unallocated cases]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 30/60
AArch64: Add stubs for a64 specific helpers

We will need helpers that only make sense with AArch64. Add
helper-a64.{c,h} files as stubs that we can fill with these
helpers in the following patches.

Signed-off-by: Alexander Graf <agraf@suse.de>

From Alexander Graf <agraf@suse.de> aarch64 series 13/60
target-arm: aarch64: add support for 2-src data processing and DIV

this patch adds support for decoding 2-src data processing insns,
and the first users, UDIV and SDIV.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder adding the 2-src decoding level,
          always zero-extend result in 32bit mode]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 44/60
target-arm: aarch64: add support for 2-src shift reg insns

this adds 2-src variable shift register instructions
C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 45/60
target-arm: aarch64: add support for 1-src data processing and CLZ

this patch adds support for decoding 1-src data processing insns,
and the first user, C5.6.40 CLZ(count leading zeroes).

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder, simpler path for 64bit form,
          reuse 32bit helper for 32bit form]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 47/60
target-arm: aarch64: add support for 1-src RBIT insn

this adds support for the C5.6.147 RBIT instruction.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder, use bswap64,
          make RBIT part standalone from the rest of the patch,
          will handle REV in a separate patch]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 46/60
target-arm: aarch64: add support for 1-src REV insns

this adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 46/60
target-arm: aarch64: add support for bitfield insns

this patch supports C3.4.2 Bitfield instructions
SBFM, BFM, UBFM.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 31/60
host-utils: add clrsb32/64 - count leading redundant sign bits

this patch introduces wrappers for the clrsb builtins,
which count the leading redundant sign bits.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
target-arm: aarch64: add support for 1-src CLS insn

this patch adds support for the CLS instruction.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From the SUSE patches
target-arm: aarch64: add support for logical (immediate) insns

this patch adds support for C3.4.4 Logical (immediate),
which include AND, ANDS, ORR, EOR.
It also includes a way to access the registers when
register 31 means SP.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder, minor function renaming,
          removed a TCG temp variable]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 29/60