STM32F0: Turn on PLL clock source when asked to

The STM32F05xxx/06xxx manual describes on p.98 (Sec 7.4.1) the RCC_CR
register, on which it says that bit 24 is the PLLON bit which has to be
enabled before using the PLL. This causes the PLL to be enabled with
rcc_osc_on(PLL).
STM32F0: Fix PLL multiplication factor for 48MHz setup

It was set to overclocking configuration!
STM32F0: Set RCC_CFGR register before setting the PLL multiplier

For unknown reasons, setting the registers in the reverse order does not cause
the PLL to work properly, this is tested on an STM32F0DISCOVERY board.
STM32F0: Fix the PLL multiplier table

The value '6' was twice in the table and all higher frequencies are
shifted. The values are now fitting the table in 'STM32F05xxx/06xxx advanced
ARM-based 32-bit MCUs', page 101.

PLL frequencies have been measured by selecting

    rcc_set_mco(RCC_CFGR_MCO_SYSCLK);

and measuring the output with an oscilloscope. 8, 16, 24, 32, 40 and 48 MHz
work fine from the HSI base.