patch: add tripndroid vibration driver
board-endeavoru: use tripndroid vibration driver
tegra3_clocks: stop this useless warning with log filling
net: disable iptables debug
tegra3_throttle: remove no_thermal_throttle_limit
arm: set HZ to 100
arm: tegra: usb_phy: set vbus_reg to NULL

Setting vbus_reg to NULL if regulator get
fails.

Bug 1047065

Change-Id: I574f58d46f226d70034a4f363103fd9763482292
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/131759
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
tegra3_clocks: update and extend cpufreq tables with steps of 100mhz
tegra3_clocks: update cpu_lp clk for steps of 100mhz
tegra3_clocks: update emc_to_cpu_ratio for the new 100mhz steps
cpu-tegra: set correct freq for new freq tables
tegra3_clocks: set correct value for mselect clk
tegra3_clocks: set correct freq for emc_balance_threshold
cpu-tegra3: set correct freq tables when using BEST_TRADE_HOTPLUG
usb: ehci: tegra: Fix Slab corruption error

Give ownership of the DMA buffer back to the processor first and
then free the buffer. Otherwise processor won't be able to
access the dma mapped buffers and this would lead to slab
corruption.
When the DMA buffer is freed without a call to dma_sync_single_for_cpu(),
the kernel won't be able to set the buffer as POISON FREE and when we
acquire this memory back again the kernel will start printing slab
corruption output as the memory is not set to POISON FREE

Bug 1017884
Bug 1018161
Reviewed-on: http://git-master/r/#change,122151
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>

Change-Id: I00d6cb185cd2314cccb56f968eb0a05288588c13
Reviewed-on: http://git-master/r/122390
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
(cherry picked from commit 642d37a0eee196d0ce811dd11bb7af5ba281ee3a)

Signed-off-by: Peter Zu <pzu@nvidia.com>
Change-Id: I3ff611a3674536a93233da53488840fb77c5d4ef
Reviewed-on: http://git-master/r/123470
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arch: arm: pcie: init TXBA registers

Setting default values in TXBA registers to avoid
unfair arbitration between downstream reads and
completions to upstream reads

Bug 1027024

Change-Id: I87763817b7974127f93fa18270b5245a54fc6676
Signed-off-by: krishna kishore <kthota@nvidia.com>
Reviewed-on: http://git-master/r/120359
Tested-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
media: video: tegra: Don't overwrite avp outbox

Before writing a new value in avp outbox register ensure the last
value written in it has been read by AVP. If AVP has not yet read
the current value in avp outbox register then wait until it is done.

Bug 1054421

Change-Id: Ie1f024969d9fcb87cf6f88b8ee3b557874eb310c
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/139406
(cherry picked from commit ecd44726ca121df4697044f5e0398aa75106ff63)

Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Change-Id: Ie01542d9ce27fff87d2a9fc5aec5d9310ed0583d
Reviewed-on: http://git-master/r/141227
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Niranjan Wartikar <nwartikar@nvidia.com>
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
GVS: Gerrit_Virtual_Submit
tegra3_clocks: increase cpu clock limits
arm: tegra: set core to 0.95V in LP1
board-endeavoru-power: settings for LP1 0.95V CoreV