csr/SRAM: prefix page register with memory name
fhdl/autofragment: FModule
fhdl/autofragment: bugfixes + add auto_attr
bus/csr: support memories with larger word width than the bus (read only)
fhdl/verilog: tristate outputs are always wire
csr/SRAM: support for writes with memory widths larger than bus words
Use common definition for FinalizeError
fhdl/autofragment: empty build_fragment by default
fhdl/autofragment: fix submodules
fhdl/tools/flat_iteration: generalize
fhdl/autofragment: remove legacy functions
migen/fhdl/autofragment: factorize
bank/description: AutoReg
bank/csrgen: BankArray
bank/description/AutoReg: check that get_memories and get_registers are callable
fhdl/module: replace autofragment
bus/asmibus: use fhdl.module API
bank/eventmanager: use module and autoreg
Fix Register name conflict between Pytholite and Bank
cdc & fifos refactoring using MultiRegImpl & Synchronizer