fix register operand with cross path
display of data path T1 or T2
fix ldw dinc opcode display
fix dinc format ldw opcode decoding
fix smvk8 instructions constant signedness
fix decoding of dpp post-decrement variant
fix flag correctness in dpp/stw opcode
fix dind register offset decoding
fix smvk8 constant decoding
fix l3i format constant decoding
fix Unop opcode cycle count decoding

The NOP 16 bits opcode formats seems to encode the cycle count as
cycle count = N3 + 1 (as does the src field of the 32 bits opcode)
This is how the Ti disassembler (dis6x) does decode it.
cleanup: remove debuging display
cleanup: add missing #undef in header files
cleanup: homogenize abort message format
cleanup: suppress '#' prefix in hardwired cst operand values
cleanup: suppress '<' & '>' around compact insn
cleanup: restore base 10 constant display
cleanup: restore original empty lines