Major Revision. Redesigned and replaced all code. The new FPGA code is written in VHDL (versus Verilog), well commented, and has been tested throughly. Removed unnecessary files and code to reduce bloat in the repository. The USRP to ML605 LVDS interface completely implemented.

Notable changes:

smm
- Removed and replaced with new MicroBlaze subsystem

microblaze
- Added new MicroBlaze subsystem
- Removed old MicroBlaze subsystem smm as the old code did not fit properly with the redesigned network communication components and USRP control logic

main.c
- Completely rewritten to support redesigned network communication and USRP control logic changes
- Added debug menu allowing network configuration changes (IP address, port addres, etc) and setting the USRP mode (send ADC data, send test sinewave, etc)

top_crush.ucf
- Updated to reflect new LVDS interface with USRP and changes in I/O names
- Implemented regenerated Ethernet core constraints

uart.vhd
debounce.vhd
edge_detect.vhd
saturate.vhd
trunc_unbiased.vhd
fifo_36x512.vhd
fifo_8x2048.vhd
fifo_16x8196.vhd
fifo_32x8196.vhd
- Added useful miscellaneous / support components

network_inft.vhd
udp_tx.vhd
udp_rx.vhd
embedded_emac_block.vhd
reset_sync.vhd
gmii_if.vhd
- Added components to receive and transmit UDP packets

spectrum_sensing.vhd
user_block.vhd
fft.vhd
- Added components to implement spectrum sensing
Merge branch 'refs/heads/testing_lvds'