cappuccino/fetch: disallow icache refill when kill_fetch=1

Otherwise the cache might get filled with data that's
never going to be used, or worse, it might not even be
accessible.
spram: add explicit bypass logic for write-first behaviour

Even though the previouse code described write-first
behaviour, some synthesis tools can't infer RAMs as write-first
when described like this (xilinx), while some add bypass logic to
behave like the code describes (altera).
By describing the RAM as read-first and then explicitly adding
the bypass logic, the same behaviour should be achieved from
different tool vendors.