Add read_cpu_reg_sp helper.
translate-a64.c: add new-line to log message
translate-a64.c: dump subject pc on unalloc enc

This turns out to be fairly handy when you are trying to figure out how
far into the binary you have got.
translate-a64.c: add a debug helper trace macro

This just makes it easier to drop TRACE_DECODE statements all over the
place instead of fprintfs.
translate-a64.c: add load/store helpers for GPRs

This adds the functions do_gpr_ld and do_gpr_st which are used for
generic load and store implementations. The load implementation also
takes into account if the operation is signed or not.
translate-a64.c: add ext_and_shift_reg helper

A number of the instructions offer a chance to extend and shift a
register value before use.

from Alexander Graf <agraf@suse.de> aarch64 series 15/60
from Alexander Graf <agraf@suse.de> aarch64 series 60/60

---

v3 -> v4 (ajb):
   - Take explicit TCGv_i64 reg for source
target-arm: aarch64: add support for add and addi

This patch combines two of the original series for generic add
implementation support.

from Alexander Graf <agraf@suse.de> aarch64 series 15/60 (- extended)
from Alexander Graf <agraf@suse.de> aarch64 series 27/60

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

v2 -> v3:

      - use extract32/sextract32 instead of get_bits and get_sbits
      - open code get_reg()

v3 -> v4 (ajb):
      - removed the flag handling helpers, stubbed out TCG equivalent
      - streamlined the generation to avoid duplication

v4 -> v5 (ajb):
      - used Claudio's common add_with_carry for flag ops
      - common as much as possible between addi/add
      - removed extraneous diagrams
      - documented the add (extended register) stub

v5 -> v6 (ajb):
      - drop add_with_carry for now

v6 -> v7 (ajb):
      - fixed dodgy tcg generation.

v7 -> v8 (ajb):
      - fixed merge conflicts with cpu_reg_sp()
      - used Claudio's generic flag helpers
      - add ext_and_shift_reg helper for extension
      - rename disas->handle for actual implementations
      - include add_sub_extended_reg

v8 -> v9 (ajb):
      - actually use extended register for offset

v9 -> v10 (ajb):
      - add CC support to add_sub_reg

v10 -> v11 (pmm):
      - split arith_CC into gen_add/sub_cc functions
      - rewrite with newer version of flag code

v11 -> v12 (ajb):
      - move to using the new read_cpu_reg helper.
target-arm: aarch64: add support for stp (store pair)

This patch support basic GPR based store-pair instructions and includes
the generic do_gpr_st() function for store routines.

from Alexander Graf <agraf@suse.de> aarch64 series 11/60

---

v2 -> v3:

      - use extract32/sextract32 instead of get_bits and get_sbits
      - drop get_reg()
      - open code get_reg()

v3 -> v4
      - split from bigger patch (non vector)
      - better naming?
target-arm: aarch64: add support for movi

This patch adds emulation for the movi instruction. This includes the
various movn, movz and movk forms.

Signed-off-by: Alexander Graf <agraf@suse.de>

---

    v2 -> v3:

      - use extract32/sextract32 instead of get_bits and get_sbits
      - open code get_reg()

    v3 -> v4 (ajb):

       - applied RH's constant folding comment
       - move cpu_reg allocation to top
target-arm: aarch64: add support for ld/st unsigned imm

This adds support for the basic non-vector form of ld/st with and
unsigned immediate offset. This was split from the original patch from
Alexander due to re-factoring due to the changes in the decoder.

from Alexander Graf <agraf@suse.de> aarch64 series 41/60

---

v3 - v4 (pmm):
   - hoisted is_vector test into function
target-arm: aarch64: add support for ld lit

Adds support for Load Register (literal).

from Alexander Graf <agraf@suse.de> aarch64 series 40/60
target-arm: aarch64: add support for ld/st with reg offet

This adds support for the load/store forms using a register offset. This
was split out from the original patch due to re-factoring changes.

from Alexander Graf <agraf@suse.de> aarch64 series 41/60

---

v3 -> v4 (ajb):
   fixed reg extension

v4 -> v5 (pmm):
   moved is_vector test into handle func
   fix invalid asset on opt==6
target-arm: aarch64: add support for ld/st with index

This adds support for the pre/post-index ld/st forms with immediate
offsets. This was split out of the original patch due to re-factoring
changes.

from Alexander Graf <agraf@suse.de> aarch64 series 41/60

---

v3 -> v4 (ajb)
   - fix ld/st reg indexed_imm to correctly extend and shift

v4 -> v5 (ajb):
   - fix silly bug with extracting register

v5 -> v6 (pmm):
   - move is_vector test into handler.
target-arm: aarch64: add support for ldp (load pair)

This uses the existing GPR load routines to do the actual load. This was
split out from the more substantial ldarx implementation.

from Alexander Graf <agraf@suse.de> aarch64 series 12/60

---

v3 -> v4 (pmm):
   - Fix offset calculation in ldp
target-arm: aarch64: add support for svc instruction

This patch adds emulation for the syscall (svc) instruction.

Signed-off-by: Alexander Graf <agraf@suse.de>

---

v2 -> v3:

  - use extract32/sextract32 instead of get_bits and get_sbits

v3 -> v4 (ajb):

  - ported to new decode skeleton

v4 -> v5 (ajb):

 - fixed stupid decode error

v5 -> v6 (ajb):
 - fix svc from peters tree.
target-arm: Support fp registers in gdb stub

Register the aarch64-fpu XML and implement the necessary
read/write handlers so we can support reading and writing
of FP registers in the gdb stub.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: load/store fp regs support

This patch adds do_fp_st() and do_fp_ld() functions for
loading/storing FP register contents, and adds decode of
the vector version of the imm12 unsigned immediate ld/st.

It also fixes up in passing some tcg temp leaks in the
handle_ldst_reg_unsigned_imm() decode.

This should probably not really be squashed since it's
a fair size patch, but probably most of the changes to
handle_ldst_reg_unsigned_imm() itself should be.

-- PMM
ldaxr &co

quick hack version from the suse patchset patch 12/60

I've fixed up the decoding but this is a no-op version
of exclusives so is definitely not upstreamable. Needs
rewrite.
3 source dp insns (suse patchset code)

SuSE patchset 49/60 code, stuffed into new decoder
Cleaned up to match current fn name conventions and the
basic code looks good to me, so:

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

TODO fix up attributions, commit messag
target-arm: Add 'unscaled immediate' ld/st

Add the 'unscaled immediate' ld/st. This goes in
with the other imm9 load/store formats.

I suspect we're going to want to fold the 'load/store unprivileged'
insns into the same imm9 decode, so I have left the door open for that.
However since we shouldn't see those for userspace code we can ignore
it for the moment.

-- PMM