Fixed bug in PWM generation spotted by Oliver Lee.

The problem manifested itself when commanding 100% duty cycle.  In
this situation, the 16-bit CCR register was being set to ARR + 1, and
ARR was set to 0xFFFF, so this overflows the 16-bit register and
effectively gets set to 0x0000, which leads to 0% duty cycle rather
than 100% duty cycle.