[FIX] Add enable port to DPRAM library components

- Add enable port to each port.
- Fix init file assert in Xilinx architecture.

Change-Id: Ib55399e00040c94beea9c31817d2aed0ec7da67e
Reviewed-on: http://brateggevoat1/gerrit/1435
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FEATURE] Add simplex DPRAM library component

The simplex DPRAM component provides one write and one read port.

Change-Id: I1f798d5690cedbd99f826509dde035ec9df85733
Reviewed-on: http://brateggevoat1/gerrit/1423
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Add host interface documentation

- Add doxygen documentation for source files.
- Add wavedrom waves
- Add scripts to generate documentation

Change-Id: I3eded64181bbd78af4823a9fc3af5a11e1adadd1
Reviewed-on: http://brateggevoat1/gerrit/1418
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>