Changed Readable's read method to return a Signal.
Separated assignments from wires.
Added inputs and outputs to RTL, and functions to add them.

- Verilog currently ignores them.
Verilog now generates module headers.
Removed Handshake interface and cleaned up FIFO example.
Minor bugfix for Pipe interface.
Added some simple stream combinators to Channels.
Added Sink class and streaming operators between sources and sinks.