Changes Wb_latch to use synchronous ACK
Changes Wb_Register to use synchronous ACK
Reduces timeout value in WB_M
Increases number of laves to 5
Adds seperate read and write strobe/ack signals and sets the error output to be the address in place of the signal 0xEEEEEEEE
 Applies many changes, all of which are to account for the new wb_latch primitive, also allows user defined addressing based on the constant user_addr
Renames GPIO_STREAM to GPIO_AUX, also updates IP CORE to include changes made to core
Updates dcores library to include new wb_test_slave_ip core, also updates GPIO_CONTROLLER_IP core