Continuing with memory tests.
Noticed error in memory read logic; detailed in comments of ControlLine class (the memory read doesn't reach the CPU -> routes back to memory and causes an error with an address of -1, which ought to signal transfer to MBR.
Updated MBR class to prepare for change in memory read logic.
Added mock MBR object to ControlLine class to allow for testing of memory read (read is implemented by using system bus to place value read from memory onto control line, which is then passed to MBR).
Added MBR test (MBR needs testing in order to test Memory read, as MBR is the read destination).
Initial testing of MBR complete and successful.
Identified redundancies in Address and Data line usage via control line; it may be an idea to keep them in place to facilitate GUI, or to delete them in favour of simple fields of type Data (for data line) and type int (for address line) in SystemBus, thus reducing code that doesn't actually do anything.
Updated comments (with design considerations affecting System Bus).