immu: add support for hardware tlb reload

Instead of generating tlb miss exceptions, walk the page tables
automatically.

It should be noted that instead of following the arch
specification on the layout of the page table entries (PTE),
the layout specified by the openrisc Linux port has been used.
The most notable difference is that in the arch specification,
it is stated that the protection bits should be looked up from a table,
and an index to that table should be in the PTE.
In Linux, the protection bits are instead embedded directly in
the PTE.
cappuccino/lsu: use fsm to control external bus accesses

Gives a bit more control over when and how the external bus
accesses are initiated.
Main motivation is for upcoming support for dmmu hw tlb reloads,
where the actual bus access will take place here in the lsu.
It also makes it more in line how things are done in the fetcher,
and enables the possibility to move the cache refill bus access
logic from the cache into the lsu.
dmmu: add support for hardware tlb reload

Instead of generating tlb miss exceptions, walk the page tables
automatically.

It should be noted that instead of following the arch
specification on the layout of the page table entries (PTE),
the layout specified by the openrisc Linux port has been used.
The most notable difference is that in the arch specification,
it is stated that the protection bits should be looked up from a table,
and an index to that table should be in the PTE.
In Linux, the protection bits are instead embedded directly in
the PTE.
Propagate FEATURE_xMMU_HW_TLB_RELOAD to top level