XXX debug hack
WIP: freedreno: more compiler
WIP: freedreno: prepare for a3xx
WIP: freedreno: more compiler
WIP: freedreno: more compiler
WIP: freedreno: more compiler
WIP: freedreno: more compiler
compiler.. more NOP's..

Need a more clever way to handle this.. it seems like we need to ensure
at least 6 instruction slots between a "simple" ALU instr writing to a
register, and a "complex" cat4 instr using that register as a source.
Not sure why there isn't a sync "(ss)" bit, like in the other direction,
but perhaps the simple ALU instructions take a more predictable number
of cycles?

If we were a bit clever, we would track how many instructions ago a
register was written, and avoid inserting a huge number of nop's.  OTOH
maybe we just deal with that in an optimization pass?  Not really sure
what the best way to handle scheduling would be.
compiler.. avoid const in cat3 src1

It doesn't actually work.  Blob compiler never seems to use a const in
src1 position.. although there does seem (according to disassembler
hidden in libllvm-a3xx.so) to be a bit to indicate that src1 is a const.
Not sure if this is a hw bug, or simply that the disassembler lies.
compiler, fix handling of (ss) bit

regmask_set() needs to come after the last add_src_reg(), otherwise we
trigger setting '(ss)' flag on the current instruction if one of the
src's is the same as the dst.
more a3xx..
compiler.. synchronize texture fetches properly