dvisampler: pack pixels in pixel clock domain to improve performance
videomixer: fix stray DMA detection
add L2 cache size in identifier + function to flush L2
bios: flushl2 command
videomixer: flush L2 after CPU framebuffer write
videomixer: add more video modes
videomixer: reduce debug output
framebuffer: unpack memory words in pixel clock domain for better perf
dvisampler: expose PLL DRP to CSR
framebuffer: expose PLL DRP to CSR
dvisampler: hold PLL in reset when disabled
videomixer: add PLL control code
videomixer: add PLL dump command
videomixer: reconfigure PLL on resolution change
videomixer: stick to 20x PLL configuration as 10x causes traditional spartan6 weirdness
dvisampler: transfer the last word in frames correctly
Revert "framebuffer: reset VTG"

This reverts commit 6cb18f5ce3c9c63250cfbe738b84ec7beb1a9412.

Conflicts:
	misoclib/framebuffer/__init__.py
	misoclib/framebuffer/format.py
videomixer: select 1024x768 by default
framebuffer: fix resynchronization after resolution change
make.py: make a bit more generic

if parts of the soc are not available or not enables on a platform, do
not use their verilog cores.