Modified Victor's fill_fifo_stimulate_tb.v to fit the inputs/outputs i used for the module. I'm not sure what fill_half_fifo_I was supposed to be used for (is that what would eventually be hsync%64?). Using a fill_half_fifo_I signal like you suggested might be more convenient for testing in modelsim whereas the way I wrote the fsm, I compute hsync%64 within the module to get the half_full signal, so it's not an input.

We also need to set the parameters like FRAME_BASE_ADDR and LINE_STRIDE in the tb file, i just left is blank for now.

Also added clock to FSM module (oops, I missed that first time around).

Will compile and test tomorrow.