EHCI: HSIC: Add support to vote for SVS digital voltage

HSIC HW can operate at SVS digital voltage when it is active.
Currently HSIC is voting for 120Mhz SFAB and 64Mhz DFAB clock
frequencies. Clock frequencies are directly proportional to SVS
voltage. If DFAB is running at 64Mhz or SFAB is running at 120Mhz
or higher SVS is not possible even though HSIC votes for it. Hence
do not vote for SFAB clock frequency and only vote for 32Mhz for
DFAB in order to allow SVS to happen. Voting for SVS voltage reduces
current consumption by 3mA in HSDPA network.

Change-Id: I8a6844efbbe90a8ea118be8450f8210717c2641b
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
(cherry picked from commit cdf7fd212e2761525c07b842eb630677777cb3e5)
(cherry picked from commit f7f368826935049e7ffdb482865c47a3badcd147)
EHCI: HSIC: Handle asynchronous interrupt properly

Runtime PM resume and asynchronous interrupt can run in parallel. When
this happens, there is a possibility of PM usage counter mismatch.
Fix this by checking the return value of pm_runtime_get() and by
disabling the USB interrupt while resuming the HSIC.

Consider asynchronous interrupt case when resuming HSIC during system
resume.

CRs-Fixed: 444883
Change-Id: I63db49d8b45a7413f9456a93c9648511ad622b4b
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>

Conflicts:
	drivers/usb/host/ehci-msm-hsic.c
EHCI: HSIC: Disable asynchronous interrupt when wakeup gpio is present

Controller can generate interrupt asynchronously in low power mode (LPM).
Enable this interrupt in USBCMD register only when wakeup gpio IRQ is
not available.

CRs-Fixed: 444883
Change-Id: I05258feb9476d1373d30645f6c750923589aa1cb
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
EHCI: HSIC: Implement new reset sequence to workaround PHY lockup issue

commit 8e6edcb (usb: ehci: Avoid phy lockup due to SOFs during port
reset) implements a workaround for PHY lockup issue during port reset.
The workaround relies on a hardware debug feature which allows driving
strobe and data lines to reset using ULPI interface.  This is not
working some times for unknown reason.

This patch implements a new reset sequence to workaround the PHY lockup
issue.  The controller drive reset signaling for ~50 msec when reset bit
is set in PORTSC register.  The controller automatically clears this bit
after finishing the reset signaling.  The software can also finish the
reset signaling any time by clearing the reset bit.

According to USB2 spec, Host controller should drive reset signaling for
50 msec for root hub ports.  But HSIC spec allows shorter reset signaling
time (20 msec).  Clear the reset bit in PORTSC register after 20 msec and
start controller immediately to send SOF.  Use controller internal timers
to achieve this.  If reset bit is not cleared in time, perform the sequence
in a loop with interrupts disabled.

CRs-Fixed: 445659
Change-Id: I6b251ced8d47b9ece4a06e58baf15c69a8bb340f
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>

Conflicts:
	include/linux/usb/hcd.h
EHCI: HSIC: Fix GPT timer count values used for resume sequence

The counter value to be loaded into GPT timer represents the time
in micro seconds minus 1 for the timer duration.  The current code
incorrectly programs the timer.  Fix it.

CRs-Fixed: 449090
Change-Id: I53eddb6b4323bbfaf0e3a1d3aaa0fb9120c70647
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>