usb: gadget: u_ether: Fix memory corruption in TX path

When data aggregation is enabled, multiple skb buffers are copied
into a single USB request buffer.  When ever a USB request queue
is failed, make sure that req->length is reset to 0.  Otherwise
when the same request is used again, the stale length field is used
to access the request buffer.  This would lead to memory corruption.

The xmit function keeps the partial request at the beginning of the
queue.  Always put the idle request at the back of the queue.

CRs-Fixed: 469436
Change-Id: Idcd31e667b0bf261ab9a88f4a34464ccdf503e1b
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
msm: clock: Move voltage scaling to prepare/unprepare

Move the voltage calls to a sleepable context so we can avoid
spinning for hundreds of microseconds with interrupts disabled
waiting for a regulator to increase. This change also paves the
way to making the clock driver into a real regulator consumer
that uses the proper regulator APIs instead of the MSM specific
rpm_vreg API.

Doing this also requires us to make clk_set_rate() a sleeping
call so that concurrent clk_prepare() and clk_set_rate() calls
are synchronized. Making clk_set_rate() sleepable also
necessitates moving the clk_set_rate() call in clock-voter.c to a
sleepable context. Do that by having clock-voter aggregate and
update the rate in prepare/unprepare instead of enable/disable
(note that enable/disable of voter clocks implicitly calls
enable/disable on the parent via generic clock code).

Now that clk_set_rate() is sleeping, call clk_prepare() and
clk_unprepare() in the clock-local code when a rate change
requires reparenting the clock. This cleans up a problem we have
where sources may be left unprepared by a clock rate switch
(hence the default true warned flag for PLLs and crystals).

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit d86d1f2d968f194e3db46bb683e370a9fa3a6037)

Conflicts:

	arch/arm/mach-msm/clock-local2.c

Change-Id: Ie5bbb17537d5b33de92f8ea1c2da6070b18c14f1
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
msm: clock-pll: Update PLL enable sequences for new processes.

The PLL enable sequences across certain chipsets are
different due to differing manufacturing processes.
Update the PLL enabling sequences to reflect these
differences.

Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
(cherry picked from commit 6da35d33d512b4dcb92ec68cf1df728da33e3381)

Conflicts:

	arch/arm/mach-msm/clock-8960.c

Signed-off-by: Dhivya Subramanian <dthiru@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
(cherry picked from commit 62ec83d7ee4739844746b81897615e499642da35)

Change-Id: I42738f570e40e6d73550030da7219b24ab65dc0c
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
clock-8960: partially revert GPU OC for new CAF updates

Signed-off-by: faux123 <reioux@gmail.com>
msm: clock-8960: Add support for 8064v2 and 8064ab.

Adjust frequency tables and voltage limits for both v2 and ab
changes.

Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
(cherry picked from commit b7c777ac16dfff010cb92b5d3347436859d3302f)

Conflicts:

	arch/arm/mach-msm/clock-8960.c

Signed-off-by: Dhivya Subramanian <dthiru@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
(cherry picked from commit 40d13ce3afe5771d2b78bfbf862d87459f541e8b)

Conflicts:

	arch/arm/mach-msm/clock-8960.c

Change-Id: Id662c9480840f301f4111e8f6744b53869f8e3c7
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
msm: clock-8960: Disable SMMU SFPB hardware clock gating.

Disable hardware clock gating for the SMMU ahb interface as
testing has shown that having it enabled leads to random lock ups
in the multimedia subsystem.

Signed-off-by: David Garibaldi <dgaribal@codeaurora.org>
(cherry picked from commit f69836a0bd51be3071b943e16112e69608c6d15d)

Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
(cherry picked from commit 6bba065fd3d78061a8a043d707eea8eac9b218cb)

Change-Id: Ie1265f10a27e58c19f1bdf5decd503ca1e933cf2
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
msm: clock-8960: Add core clock for second gfx3d iommu on 8960ab.

The 8960ab has two gfx3d iommus one of which was missing.
Also add a dependency on gfx3d_axi_clk for 8960ab.

Signed-off-by: Joel King <joelking@codeaurora.org>
(cherry picked from commit 9af070bb08217aa3668be5a1ff7ab3cc7964c64c)

Change-Id: Ic45910df027a02766a1841b825c16ea7413d65ca
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
msm: clock-local: Add PXO rates for LPASS clocks on 8660, 8960, 8930, 8064

LPASS clock are enabled out of reset on these SoCs, with PXO selected
as their undivided source. Because PXO rates are not present in the
frequency tables however, these clocks fail to handoff with reason
'HANDOFF_UNKNOWN_RATE'. As a result, clock_late_init() does not attempt
to disable these clocks in lateinit.

Add PXO rates to the LPASS frequency tables so that handoff succeeds
and, in lateinit, disables them if they are not used.

(cherry picked from commit ac15a37fd85089a2aef16624140a5d0a6cd1d71b)

Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Change-Id: Id8d674bfa3d41316be8aa14c5cc84baa77078d23

Signed-off-by: Neha Pandey <nehap@codeaurora.org>
msm: clock-8960: Lower frequency requirements of fpb active votes

We have an active set vote for the multimedia fpb and chip fpb so
that the registers are accessible whenever the processor is
awake. Unfortunately these requests are at the highest rate
supported which is not really necessary to ensure that the buses
are clocking. Lower the rate requests to the fastest speed that
doesn't require increasing voltages to allow the chip to hit low
voltages when the processor is awake.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit 9e497f042d8525e57e11d417e9e37c2932a18dbf)

Change-Id: I3ee4926da0d953e7e31c3c64dffd11f6ee5edb72
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
clock-8960: consolidate 3d tables and re-enable GPU overclocking

Signed-off-by: faux123 <reioux@gmail.com>
msm: clock-8960: Add 1.8MHz rate to 8064's gfx3d_clk plan

This rate will be used by the 'footswitch-8x60' driver when
controlling GFX3D power.

Change-Id: Ib796114dc90b468f1c0aa014a9db699f3b854adf
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm: footswitch-8x60: Allow specification of per-fs reset delays

Custom reset rates can be specified for clocks via fs_clk_data. If
these rates are very low, then the default reset delay of 1us may
not be sufficient. Address this by allowing custom reset delays to
be specified on a per-footswitch bases.

Change-Id: Id9b9377d79436a7fe5007a8f37216a456d66ce1a
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/footswitch-8x60.c
	arch/arm/mach-msm/footswitch.h
msm: footswitch-8x60: Update 8064 footswitch_enable() sequence for GFX3D

Update 8064's GFX3D enable sequence per hardware designer recommendations
to improve system stability when responding to the inrush current event.

Differences from the standard footswitch_enable() sequence include:
 - Decreasing the reset_rate from 27MHz to 1.8MHz, and increasing
   reset_delay_us from 1us to 10us to compensate for the slower clock.
 - Enable clocks for reset propagation only after the core has been
   powered on.
 - Forcefully limit the AFAB and EBI1 clocks to a low value (decided
   by the RPM) by means of a write to the RPM_CTL RPM resource.
 - Removal of the reset toggle after powering on the core, which (while
   harmless) is not applicable to 8064.

Change-Id: I943842b56ff96b2e6077a419566d91ac184a6fda
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/footswitch-8x60.c