Xilinx block RAM conflict avoidance, etc

*  The cache is working well in simulation, but it still flakey on
   real hardware.  It was my thought that the cause was the unpredictability
   of block RAM when read & written at the same location at the same time.
   I am using inferred block RAM, and currently the Xilinx tools are
   inferring most of the RAM in READ_FIRST mode, but the second Way of
   data RAM was inferred as WRITE_FIRST.  I don't know why.

   The solution is to add a bypass path to the RAM to avoid the dirty
   data problem.  This had the added benefit of shortening a refill
   sequence by one cycle.

*  Removed the `relax' signal in the cache;  it's no longer needed.

*  Cleaned up my changes to the processor a little.  It became clear to
   me how the processor models RAM, and that no further changes are
   needed.

-  This version is still as flakey as before on real hardware.  I did
   notice that it seems to work fine when running from ROM (read-only
   block RAM), but is flakey when running from SDRAM.  It could be a
   problem with the SDRAM controller I wrote.  That controller has been
   reliable for a long while, but all accesses from the CPU were single
   word cycles, and with the cache, there are now pipelined accesses.
-  Of course, it could just be that I'm running the CPU too fast...