Add a machine code print in DEBUG() following instruction selection.

Make debugging ISel a bit easier by printing out a dump of the generated
code at the end.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197456 91177308-0d34-0410-b5e6-96231b3b80d8
Typo. s/reserved/preserved/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197457 91177308-0d34-0410-b5e6-96231b3b80d8
Make comment more explicit.

Re-reading the comment I updated in previous commit, it's better to make
it more explicit and avoid ambiguity more effectively.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197458 91177308-0d34-0410-b5e6-96231b3b80d8
Tweak lit/TestingConfig.py Py3-compatible. has_key is dead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197462 91177308-0d34-0410-b5e6-96231b3b80d8
whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197464 91177308-0d34-0410-b5e6-96231b3b80d8
Allow MachineCSE to coalesce trivial subregister copies the same way that it coalesces normal copies.

Without this, MachineCSE is powerless to handle redundant operations with truncated source operands.

This required fixing the 2-addr pass to handle tied subregisters. It isn't clear what combinations of subregisters can legally be tied, but the simple case of truncated source operands is now safely handled:

     %vreg11<def> = COPY %vreg1:sub_32bit; GR32:%vreg11 GR64:%vreg1
     %vreg12<def> = COPY %vreg2:sub_32bit; GR32:%vreg12 GR64:%vreg2
     %vreg13<def,tied1> = ADD32rr %vreg11<tied0>, %vreg12<kill>, %EFLAGS<imp-def>

Test case: cse-add-with-overflow.ll.

This exposed an existing bug in
PPCInstrInfo::commuteInstruction. Thanks to Rafael for the test case:
PowerPC/crash.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197465 91177308-0d34-0410-b5e6-96231b3b80d8
Add -mcpu=z10 to SystemZ tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197466 91177308-0d34-0410-b5e6-96231b3b80d8
llvm-config: Let directories aware of CMAKE_CFG_INTDIR.

With llvm-config.exe --bindir --libdir --build-mode, on Visual Studio 2010,

In build tree:
  (OBJ_ROOT)/bin/MinSizeRel
  (OBJ_ROOT)/lib/MinSizeRel
  MinSizeRel

In installed tree:
  (INSTALL_PREFIX)/bin
  (INSTALL_PREFIX)/lib
  MinSizeRel

This is enhancements since r196283.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197467 91177308-0d34-0410-b5e6-96231b3b80d8
Mark vastart_save_xmm_regs as changing EFLAGS

The vastart_save_xmm_regs pseudo-instruction expands to a test and a
branch, so it modifies EFLAGS.  Mark it so, or else the scheduler might
place it in the middle of another test+branch.

This fixes a bug exposed by r192750, which turned on the MI Scheduler
for X86.

<rdar://problem/15627766>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197469 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "Mark vastart_save_xmm_regs as changing EFLAGS"

This reverts commit r197469.

The sanitizer and dragonegg buildbots are failing, I think because of
this change.  Reverting until I figure out why.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197481 91177308-0d34-0410-b5e6-96231b3b80d8
AVX-512: Added implementation of CONCAT_VECTORS for v8i1 vectors (by Alexey Bader).
Added implementation of "truncate" from integer type (i64/i32/i16/i8) to i1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197482 91177308-0d34-0410-b5e6-96231b3b80d8
There are no __register_frame and __deregister_frame functions 
when using structured exception handling (SEH) on Windows 64.

http://llvm-reviews.chandlerc.com/D2378

Patch by Jonathan Liu!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197483 91177308-0d34-0410-b5e6-96231b3b80d8
Fix for PR18045:
http://llvm.org/bugs/show_bug.cgi?id=18045

Short issue description:
For X86 machines with sse < sse4.1 we got failures for some
particular load/store vector sequences:

$ clang-trunk -m32 -O2 test-case.c
fatal error: error in backend: Cannot select: 0x4200920: v4i32,ch = load 0x41d6ab0, 0x4205850,
      0x41dcb10<LD16[getelementptr inbounds ([4 x i32]* @e, i32 0, i32 0)](align=4)> [ORD=82]
      [ID=58]
  0x4205850: i32 = X86ISD::Wrapper 0x41d5490 [ORD=26] [ID=43]
    0x41d5490: i32 = TargetGlobalAddress<[4 x i32]* @e> 0 [ORD=26] [ID=23]
  0x41dcb10: i32 = undef [ID=2]

The reason is that EltsFromConsecutiveLoads could emit such load instruction
both before and after legalize stage. Though this instruction is not legal for
machines with SSSE3 and lower.

The fix: In EltsFromConsecutiveLoads, if we have passed legalize stage, we
check whether nodes it emits are legal. 

P.S.: If you get failure in time from 12:00 and till 22:00 (UTC-8),
perhaps I'll slow with response, so you better reject this commit. Thanks!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197492 91177308-0d34-0410-b5e6-96231b3b80d8
Fix code sample in NVPTX examples: now it compiles to PTX and runs as expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197498 91177308-0d34-0410-b5e6-96231b3b80d8
Add some simple COFF files with Z7 debug info

These will later be used as tests for the dumper part of http://llvm-reviews.chandlerc.com/D2232

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197499 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the pointer size for the PS3 datalayout.

This will be tested from clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197501 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "Revert "Mark vastart_save_xmm_regs as changing EFLAGS""

This reverts commit r197481, recommiting r197469 with an extra fix.

The vastart_save_xmm_regs pseudo-instruction expands to a test and a
branch, so it modifies EFLAGS.  Mark it so, or else the scheduler might
place it in the middle of another test+branch.

This fixes a bug exposed by r192750, which changed the initial scheduler
to source-order as part of enabling the MI Scheduler for X86.

This re-commit changes the VASTART_SAVE_XMM_REGS custom inserter not to
try to save %flags, and adds a test that catches the bad behavior of
r197469.

<rdar://problem/15627766>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197503 91177308-0d34-0410-b5e6-96231b3b80d8
Setting the CPU in the new vaargs test

Trying to fix buildbots after r197503 (test passes locally).

<rdar://problem/15627766>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197505 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Fix off by one issue when applying a fixup.

The branch offset for a R_MIPS_PC16 relocation is indeed a 16-bit signed
immediate.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197506 91177308-0d34-0410-b5e6-96231b3b80d8
Add warning capabilities in LLVM.
This reapplies r197438 and fixes the link-time circular dependency between
IR and Support. The fix consists in moving the diagnostic support into IR.

The patch adds a new LLVMContext::diagnose that can be used to communicate to
the front-end, if any, that something of interest happened.
The diagnostics are supported by a new abstraction, the DiagnosticInfo class.
The base class contains the following information:
- The kind of the report: What this is about.
- The severity of the report: How bad this is.

This patch also adds 2 classes:
- DiagnosticInfoInlineAsm: For inline asm reporting. Basically, this diagnostic
will be used to switch to the new diagnostic API for LLVMContext::emitError.
- DiagnosticStackSize: For stack size reporting. Comes as a replacement of the
hard coded warning in PEI.

This patch also features dynamic diagnostic identifiers. In other words plugins
can use this infrastructure for their own diagnostics (for more details, see
getNextAvailablePluginDiagnosticKind).

This patch introduces a new DiagnosticHandlerTy and a new DiagnosticContext in
the LLVMContext that should be set by the front-end to be able to map these
diagnostics in its own system.

http://llvm-reviews.chandlerc.com/D2376
<rdar://problem/15515174>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197508 91177308-0d34-0410-b5e6-96231b3b80d8