s6ddrphy: improve genericity by adding wr_bitslip and dqs_ddr_alignment parameters bitslip parameter is renamed to rd_bitslip
rename milkymist-ng to MiSoC
use git commit id as version
top: set platform ID
cpuif.py: add _ADDR and _SIZE defines for each register

Signed-off-by: Robert Jordens <jordens@gmail.com>
common.mak: -Os instead of -O3, smaller bios (<32k)
s6ddrphy: drop unused outputs, shortens verilog and produces more readable warnings

Signed-off-by: Robert Jordens <jordens@gmail.com>
common.mak: specify python3
s6ddrphy: use shorter Instance argument notation
common.mak: drop the echo from the version tag finding, did not work here, use python -c
make.py: make a bit more generic

if parts of the soc are not available or not enables on a platform, do
not use their verilog cores.
spiflash: add read-only variable data width spi flash
tdcdtc: preliminary version of serdes based TDC+DTC wishbone peripheral
etherbone: add etherbone slave (= wishbone master)
lx9crg: add crg for lx9 microboard
memtest: shrink memtest space from 64M to 32M

for smaller platforms like the lx9 microboard
software/bios: temporarily disable crcbios()

fails if flash is not working
top.py, lm32_config.v, linker.ld: use static hardcoded rom for bios
remaining changes for lx9 microboard
lx9 impact script for its embedded closed source jtag