target-arm: Add support for dumping AArch64 VFP register state

When dumping the current CPU state, we can also get a request
to dump the FPU state along with the CPU's integer state.

Add support to dump the VFP state when that flag is set, so that
we can properly debug code that modifies floating point registers.

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, rebased. Output all registers, two per-line.]
Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Give the FPSCR rounding modes names

When setting rounding modes we currently just hardcode the numeric values
for rounding modes in a big switch statement.

With AArch64 support coming, we will need to refer to these rounding modes
at different places throughout the code though, so let's better give them
names so we don't get confused by accident.

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, use names from ARM ARM.]
Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
softfloat: Add float to 16bit integer conversions.

ARMv8 requires support for converting 32 and 64bit floating point
values to signed and unsigned 16bit integers.

Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Add 64bit VFP floating and fixed-point conversion helpers

With AArch64 VFP can now handle 64bit wide VFP floating and fixed-point
conversions. Add handlers for them.

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak. Split handlers into a round to zero variant and
 a round to current mode variant to ensure ARMv7 behaviour is correct.]
Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Add AArch64 "Floating-point<->fixed-point" instructions

This patch adds emulation for the instruction group labeled
"Floating-point <-> fixed-point conversions" in the ARM ARM.

Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU
(scalar, fixed-point).

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, rebased, updated to new infrastructure.
 Applied bug fixes from Michael Matz and Janne Grunau.]
Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Add AArch64 fmov (scalar, immediate) instruction

This patch adds emulation for the fmov instruction working on scalars
with an immediate payload.

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, rebase and use new infrastructure.]
Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Add AArch64 floating-point<->integer conversion instructions

Add support for the AArch64 floating-point<-> integer conversion
instructions to disas_fpintconv.

Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Rework AArch64 SIMD/FP decode skeleton

Split floating point instruction decode out into a separate function.

Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Add AArch64 "Floating-point data-processing (1 source)"

This patch adds support for the "Floating-point data-processing (1 source)"
group of instructions.

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, merged single and double precision patches,
 updated to new infrastructure.]
Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Add AArch64 "Floating-point data-processing (2 source)"

This patch adds emulation for the "Floating-point data-processing (2 source)"
group of instructions.

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, merge single and double precision patches. Rebase
 and update to new infrastructure.]
Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Add a flags parameter to VFP muladd helpers

Add a flags parameter to the VFP muladd helper routines in. For AArch32 this
is always zero but AArch64 may pass a non-zero flags value.

Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Add AArch64 "Floating-point data-processing (3 source)"

This patch adds emulation for the "Floating-point data-processing (3 source)"
group of instructions.

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, merged single and double precision patches.
 Implement using muladd as suggested by Richard Henderson.]
Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Enable AArch64 floating point literal loads

Call do_fp_ld from handle_ld_lit to handle literal loads to floating
point registers.

Signed-off-by: Will Newton <will.newton@linaro.org>