Repair tuna kernel compilation missing label

Signed-off-by: Dan Trifan <jimsth@gmail.com>
Added sysfs option to set screen_on_min_freq
With this option, the certain lack of smoothness can be counteracted when scaling_min_freq is set very low (e.g. to 192 MHz). Thanks to this option, battery savings granted by the low scaling_min_freq can be achieved, without any negative effects to the user.
The sysfs path is located at: /sys/devices/system/cpu/cpu0/cpufreq/screen_on_min_freq

Signed-off-by: Dan Trifan <jimsth@gmail.com>
optimized screen_on_min_freq behavior

Signed-off-by: Dan Trifan <jimsth@gmail.com>
Add ARM CPU topology

** This is a combination of 12 commits.
** The first commit's message is:
Add ARM cpu topology definition

(Patch accepted by Russell for 3.1:
http://www.spinics.net/lists/arm-kernel/msg131273.html)

The affinity between ARM processors is defined in the MPIDR register.
We can identify which processors are in the same cluster,
and which ones have performance interdependency. We can define the
cpu topology of ARM platform, that is then used by sched_mc and sched_smt.

The default state of sched_mc and sched_smt config is disable.
When enabled, the behavior of the scheduler can be modified with
sched_mc_power_savings and sched_smt_power_savings sysfs interfaces.

Changes since v4 :
*  Remove unnecessary parentheses and blank lines

Changes since v3 :
* Update the format of printk message
* Remove blank line

Changes since v2 :
* Update the commit message and some comments

Changes since v1 :
* Update the commit message
* Add read_cpuid_mpidr in arch/arm/include/asm/cputype.h
* Modify header of arch/arm/kernel/topology.c
* Modify tests and manipulation of MPIDR's bitfields
* Modify the place and dependancy of the config
* Modify Noop functions

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@verdurent.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>

** This is the 2nd commit message:

ARM: cpu topology: fix warning

kernel/sched.c:7354:2: warning: initialization from incompatible pointer type

Align cpu_coregroup_mask prototype interface with sched_domain_mask_f typedef
use int cpu instead of unsigned int cpu

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

** This is the 3rd commit message:

ARM: cpu topology: Add update_cpu_topology function

arch_update_cpu_topology function is called by the scheduler
before building its sched_domain hierarchy. Prepare the update
of the cpu topology masks in this function in addition to set
it in the the store_cpu_topology which is executed only once per cpu.

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

** This is the 4th commit message:

ARM: cpu topology: modify cpu topology

Modify the CPU topology policy according to the sched_mc level and the cortex family

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

** This is the 5th commit message:

ARM: scheduler: add a cpu_power function

Add an architecture specific function for setting cpu_power

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

** This is the 6th commit message:

ARM: cpu topology: Modify cpu_power according to sched_mc level

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

** This is the 7th commit message:

ARM: cpu topology: Modify cpu_power according to cpufreq

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

** This is the 8th commit message:

ARM: cpu topology: Add asym topology flag for using cpu0 1st

Modify the CPU sched_domain flags in powersave mode for using the cpu0 in ched_mc powersave mode

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

** This is the 9th commit message:

ARM: cpu topology: Add debugfs interface for cpu_power

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

** This is the 10th commit message:

sched: Ensure cpu_power periodic update

With a lot of small tasks, the softirq sched is nearly never called
when no_hz is enable. The load_balance is mainly called with
the newly_idle mode which doesn't update the cpu_power.
Add a next_update field which ensures a maximum update period when
there is short activity

Signed-off-by: Vincent Guittot <vincent.guittot at linaro.org>

** This is the 11th commit message:

ARM: scheduler: add a missing part
This fix adds a missing part in the [RFC 07/11].

Signed-off-by: Vincent Guittot <vincent.guittot at linaro.org>

** This is the 12th commit message:

sched: nohz_idle_balance

clear rq->nohz_balance_kick before returning

if idle equals CPU_IDLE, we return and could let nohz_balance_kick set
rq->nohz_balance_kick is tested in nohz_balancer_kick before triggering a SOFTIRQ on the ilb.
If this_rq->nohz_balance_kick stay to 1, the ilb will no be triggered until it wakes up and performs a normal load_balance which will clear the nohz_balance_kick

Signed-off-by: Vincent Guittot <vincent.guittot at linaro.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
GCC 4.7: set CPU type in boot/compressed/makefile

Signed-off-by: Dan Trifan <jimsth@gmail.com>
lib/sha1: use the git implementation of SHA-1

For ChromiumOS, we use SHA-1 to verify the integrity of the root
filesystem.  The speed of the kernel sha-1 implementation has a major
impact on our boot performance.

To improve boot performance, we investigated using the heavily optimized
sha-1 implementation used in git.  With the git sha-1 implementation, we
see a 11.7% improvement in boot time.

10 reboots, remove slowest/fastest.

Before:

  Mean: 6.58 seconds Stdev: 0.14

After (with git sha-1, this patch):

  Mean: 5.89 seconds Stdev: 0.07

The other cool thing about the git SHA-1 implementation is that it only
needs 64 bytes of stack for the workspace while the original kernel
implementation needed 320 bytes.

Signed-off-by: Mandeep Singh Baines <msb@chromium.org>
Cc: Ramsay Jones <ramsay@ramsay1.demon.co.uk>
Cc: Nicolas Pitre <nico@cam.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: linux-crypto@vger.kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Remove ARM SHA1 routines

Since commit c6cdf9c ("lib/sha1: use the git implementation of
SHA-1"), the ARM SHA1 routines no longer work.  The reason? They
depended on the larger 320-byte workspace, and now the sha1 workspace is
just 16 words (64 bytes).  So the assembly version would overwrite the
stack randomly.

The optimized asm version is also probably slower than the new improved
C version, so there's no reason to keep it around.  At least that was
the case in git, where what appears to be the same assembly language
version was removed two years ago because the optimized C BLK_SHA1 code
was faster.

Reported-and-tested-by: Joachim Eastwood <manabian@gmail.com>
Cc: Andreas Schwab <schwab@linux-m68k.org>
Cc: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Remove sha1.S

arm: remove stale export of 'sha_transform'

The generic library code already exports the generic function, this was
left-over from the ARM-specific version that just got removed.

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP2+: clock: Fix DPLL clock rounding

Function omap2_dpll_round_rate() succeeds only if it can find exact frequency.
But in current implmentations there are some frequencies that can't be rounded.
Function iterates frequencies that always lower than requested one.
For example 550MHz can be obtain from 38.4MHz reference by M=1375 and N=96,
but the closest MN pair that is tried is 1374/96.

It happens because of flooring scaled_rt_rp variable insted of rounding.
This patch should fix the issue.

Change-Id: Iceadcc695ac3376372b2fdaf29afe8f9454b891f
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP2+: clock: Round clock to the closest possible frequency.

Currently clock is always rounded to frequency that is <= required.
It leads to not the best divider selection if requested frequncy is
slightly lower than the closest possible frequency.

This patch makes the best possible divider to be choosen.

Change-Id: I732dbf3e2c910b041434ded0df78dd6f85b7c7f4
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
[IVAHD] Disable HWSUP mode and save power

Enabling HWSUP mode is somehow reducing the performance
of SL2 memory leading to increase in power consumption.
This patch disables it and advertises only SWSUP mode
which seems to improve performance and reduce power
consumed in AV record use-case.

Change-Id: Ie7d06b2a7a8d251820afd63bbb093fa34203c3fa
Signed-off-by: Sundar Raman <sunds@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAPDSS: DISPC: Use FIR filters other than M19

Pass correct arguments to FIR filter selection.  Previously we
always ended up selecting M19 5-tap filter.

This should improve image quality of scaled layers.

Change-Id: Iabe3219df7dcfd62c713fd92ee9c3d12221bc382
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAPDSS: DSSCOMP: efficiency improvement.

This change adds 3 local caches of objects, which are used at each flip buffer
action. In original variant kzalloc()/kfree() functions are called each time
dsscomp_gralloc_queue() function is called. This meens that slab|slob|slub
common cache is used at each frame draw action. Call to kzalloc()/kfree()
result in synchronization with other code, which uses common cache, and can
result in dips in FPS, when other code allocates/frees memory.
This change improves reliability, autonomy and efficiency of DSSCOMP module.

Change-Id: Id50778f4579309fb71318a32820b9d6441a6dac1
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: PM: OPP/Clock: Add virtual clocks for high IVA OPPs support

To get correct frequencies for IVA OPP higher than OPP100
IVA DPLL should be reconfigured.
Tesla is also supplied from the same IVA DPLL, so frequency on DSP
should be reconfigured together with IVAHD frequency.

This is achieved by adding virtual clocks for IVA and DSP.
Main logic is implemented in IVA virtual clock which sets
frequency for both IVAHD and DSP.
DSP virtual clock is just a dummy clock and it do nothing.

Necessary DSP OPP is set via IVA virtual clock by using DVFS framework feature:
if device on which OPP is set is not the primary device in voltage domain,
then constraint to the same OPP is set for primary device.
In case of DSP the primary device is IVAHD.

If switching to the lower OPP will cause IVA DPLL scaling up,
then frequency of IVA and DSP should be scaled down before DPLL.

Change-Id: I1b229f1d52f0f8bfa4f65f08221df1e1ba6194bc
[jagadeeshwar.reddy@ti.com: original patch author for 4430]
Signed-off-by: Jagadeeshwar Reddy <jagadeeshwar.reddy@ti.com>
[taras@ti.com: modified and extended for all OMAP44xx]
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP: clock: Add dummy round_rate and set_rate functions

Add functions which are going to be used by dummy virtual clocks:
long clk_dummy_round_rate(struct clk *clk, unsigned long rate)
int clk_dummy_set_rate(struct clk *clk, unsigned long rate)

Change-Id: I9bb1e886888a117548d62ef2edd9598bce2723e6
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: clock: Add 'virt_lcd_pclk' clock

Add virtual LCD pixel clock which is going to be used for DSS OPPs

Change-Id: Ia42668873d4dbe75deef22e97cec449a00f987d0
Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com>
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: OPP: Add DSS OPPs

To generate pixel clock rate higher than 93MHz
DSS has to scale VDD_CORE to at least OPP100 level.

This patch adds two DSS OPPs, for DSS to be able
to control minimum VDD_CORE level.

Change-Id: I98eab1c3b56fcf41026b742cb43c8155b68dd5c4
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>

Conflicts:
	arch/arm/mach-omap2/opp4xxx_data.c

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: PM: Handle LPDDR CLK IO errata during suspend/idle

There is a HW bug in CMD PHY which gives ISO signals as same for
both PADn and PADp on differential IO pad, because of which IO
leaks higher as pull controls are differential internally and
pull value does not match A value.
Though there is no functionality impact due to this bug, it is
seen that by disabling the pulls there is a savings ~500uA in
OSWR, but draws ~300uA more during OFF mode.

To save power during both idle/suspend following approach taken:
 1) Enable WA during boot-up.
 2) Disable WA while attempting suspend and enable during resume.

CDDS no: OMAP4460-1.0BUG00291
(OMAP official errata ID yet to be available).

Change-Id: Ic39f17be50ff602c71e714b05af3811b35c1a67f
Reported-by: Logan Lee <hklee@ti.com>
Signed-off-by: Shashi Shekar B.S. <shashi.shekar@ti.com>
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAPDSS: DSS: Scale DSS OPP according to pixel clock rate

Before enabling pixel clock DSS should set its OPP
for OPP framework to set correct VDD_CORE voltage level.

When pixel clock is disabled DSS can set the lowest OPP.

Change-Id: Ia1459614ae306dba9b048b149e474442e2880bba
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>

Conflicts:
	drivers/video/omap2/dss/dsi.c

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4460: TWL/TPS data: update retention voltages to spec rev 0.3

Update retention voltages from Operating Conditions Data Manual
Addendum Revision 0.3 (August 2011).

OFF voltage is also updated as per requirement of 4460 OFF mode
conditions.

Change-Id: I558f0a483911b2616d0a19f9272a03258e35904a
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>

Conflicts:
	arch/arm/mach-omap2/omap_twl.c

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAPDSS: DISPC: Pipe threshold sizes power optimization.

This patch changes the calculation of thresholds and sets low
threshold to half of buffer size for OMAP4. The memory will
able to sleep between transactions to dss because dss will
read by big chunks.

boype: Also removed dispc_calculate_threshold function, as it is no longer used.

Backport from TI omapzoom kernel 3.4 repo, based upon:
http://git.omapzoom.org/?p=kernel/omap.git;a=commit;h=cd99eb345e1ad26ffbc665f46ea917dad762937b

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAPDSS: drop small YUV encoded frames on OMAP44xx

OMAP44xx has hardware limitation: in stall mode, when the frame pixel size
is less than output SyncFifo depth(16), DISPC hangs without sending any data.
Simple workaround is to drop such frame, as cases when YUV frames of this size
are very rare.

Change-Id: I31dc262b07a52b66209c093f136ad2bac66f9439
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>