UPSTREAM: clk: exynos4: Remove SoC-specific registers from save list

Current clock save list is shared for all Exynos4 SoCs, so it must
contain only registers present in all supported SoCs, because accessing
unavailable registers might have undefined effect.

This patch removes registers specific for particular SoCs from shared
save list, as they should be supported by separate SoC-specific lists.

NOTE: exynos4 CCF patches picked to avoid conflicts

BUG=chrome-os-partner:19772
TEST=None

Change-Id: Ic83b8e22dd0d62e14948c8369d6e73dd61647952
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 0f1fce908efb2aa76b713d424b422f117376a04a)
Reviewed-on: https://gerrit.chromium.org/gerrit/56961
UPSTREAM: clk: exynos4: Add E4210 prefix to LCD1 clock registers

This patch adds E4210 prefix to all registers related to LCD1 clock
domain, because they are present only on Exynos4210.

NOTE: exynos4 CCF patches picked to avoid conflicts

BUG=chrome-os-partner:19772
TEST=None

Change-Id: I8d7f63e6654998ed41fa929ba38998c3ecc9bcaa
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 7406ee7c2a31c0fad0d8062de93fcb58d1fa498c)
Reviewed-on: https://gerrit.chromium.org/gerrit/56962
UPSTREAM: clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register

This definition is specific for Exynos4210 (which has another location
than the same register on Exynos4x12 SoCs) and so needs appropriate
prefix.

NOTE: exynos4 CCF patches picked to avoid conflicts

BUG=chrome-os-partner:19772
TEST=None

Change-Id: I947fdec2fe6acd3022e4c7b462d300dfcc0dce32
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 1f1f326763cf2352173eca1fc4116de6950ba773)
Reviewed-on: https://gerrit.chromium.org/gerrit/56963
UPSTREAM: clk: exynos4: Remove E4X12 prefix from SRC_DMC register

This register is present on all Exynos4 SoCs and so the prefix is
misleading.

NOTE: exynos4 CCF patches picked to avoid conflicts

BUG=chrome-os-partner:19772
TEST=None

Change-Id: I9fb26451340d2684e9e53b139dd76f615ee8b191
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit b950622bddc1c15f1e17041f1aec5816912ccca5)
Reviewed-on: https://gerrit.chromium.org/gerrit/56964
UPSTREAM: clk: exynos4: Add missing registers to suspend save list

This patch adds missing clock control registers to the list of registers
that should be saved across system suspend.

NOTE: exynos4 CCF patches picked to avoid conflicts

BUG=chrome-os-partner:19772
TEST=None

Change-Id: Ifc5ab1b5b4d69ca31d5a0fd6b7ba8607360ddde8
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit fb948f74ce05c5540f9ad7e92242e1c931f7c2f6)
Reviewed-on: https://gerrit.chromium.org/gerrit/56965
UPSTREAM: clk: exynos4: export clocks required for fimc-is

This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1,
ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1,
DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are
available to the consumers (Exynos4x12 FIMC-IS subsystem).
While at it, indentation of the mux clocks table is
corrected.

NOTE: exynos4 CCF patches picked to avoid conflicts

BUG=chrome-os-partner:19772
TEST=None

Change-Id: I3f5e4c968d9f6697887300e547d153b9398610aa
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit cdbf618ab8a326cb3bdc65e8adb74bac9c347e64)
Reviewed-on: https://gerrit.chromium.org/gerrit/56966
UPSTREAM: clk: exynos: prepare for multiplatform

The new common clock drivers for exynos are using compile
time constants and soc_is_exynos* macros to provide backwards
compatibility for pre-DT systems, which is not possible with
multiplatform kernels. This moves all the necessary
information back into platform code and removes the mach/*
header inclusions.

NOTE: exynos4 CCF patches picked to avoid conflicts

BUG=chrome-os-partner:19772
TEST=None

Change-Id: I0b80309cae590e3b0ab1c78541f646a7662dd829
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 25e56eba0ae783fc5b66d50c68826f276e8bd8c6)
Reviewed-on: https://gerrit.chromium.org/gerrit/56967
UPSTREAM: clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}

In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide)
instead of RATIO bit-field (4-bit wide) for dividing clock rate.

With current common clock setup, we are using RATIO bit-field which
is creating FIFO read errors while accessing eMMC. Changing over to
use PRE_RATIO bit-field fixes this issue.

dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020)
mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0
end_request: I/O error, dev mmcblk0, sector 1

WARNING:
* This CL will break things on snow.  See the CQ-DEPEND for the fix.

CQ-DEPEND=CL:If62c45df1aa934cb465ad3cda9413a9a7e6dca45
BUG=None
TEST=Boot up snow

Change-Id: I040766dbba7ab00ca3f040e8f133fbae8a22b03e
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
CC: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 688f7d8c9fef621c53c7b385ff6baf62bcb6b077)
Reviewed-on: https://gerrit.chromium.org/gerrit/56971
Reviewed-by: Simon Glass <sjg@chromium.org>
UPSTREAM: clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}

commit 688f7d8c9fef ("clk: exynos5250: Fix divider values for
sclk_mmc{0,1,2,3}") incorrectly sets the divider for sclk_mmc{0,1,2,3}
to fix the wrong clock value. Though this fixed issue with Arndale,
it created regressions for other boards like Snow.

On Exynos5250, sclk_mmc<n> is generated like below (as per the clock
names in drivers/clk/samsung/clk-exynos5250.c)

mout_group1_p ==> mout_mmc<n> ==>
		div_mmc<n> ==> div_mmc_pre<n> => sclk_mmc<n>

Earlier div_mmc<n> was set as the parent for sclk_mmc<n>, hence
div_mmc_pre<n> was not getting referred in kernel code and depending
on its value set during preboot, sclk_mmc<n> value was different for
various boards.

Setting the correct clock generation path should fix the issues
reported in above referenced commit. The changes committed during the
earlier patch has also been reverted here.

BUG=None
TEST=Boot up snow

Change-Id: If62c45df1aa934cb465ad3cda9413a9a7e6dca45
Reported-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 37746c9a2dd28d52790dd84267b848c087a63b2e)
Reviewed-on: https://gerrit.chromium.org/gerrit/56972
Reviewed-by: Simon Glass <sjg@chromium.org>
UPSTREAM: clk: samsung: Remove unimplemented ops for pll

Unimplemented clock operations should be simply omitted instead of returning
error values.

This patch removes unimplemented PLL operations to fix problems caused
by returning error code in round_rate callback.

BUG=chrome-os-partner:19772
TEST=Built and booted on snow and ares.
Tested by setting and getting rate for MALI, Audio and FIMD

Change-Id: I55027b239a448500fc5a2c5ed07fbf7d0eabaae0
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit a8b5a39ecbbe5b00554b5025af4464abe12bfcd8)
Reviewed-on: https://gerrit.chromium.org/gerrit/56933
clk: samsung: Use clk->base instead of directly using clk->con0 for PLL3xxx

To factor out possible common code, this patch unifies the clk strutures used
for PLL35xx & PLL36xx and usues clk->base instead of clk->con0.

Picked from:
       https://patchwork.kernel.org/patch/2629751/

WARNING: Without the patch referred to in the CQ-DEPEND exynos5420
devices won't work properly.  Patches are separated so we can pick the
one sent upstream with no modifications.

CQ-DEPEND=CL:I73932825fb8a2b98c662c68a95b2700f808784ef
BUG=chrome-os-partner:19772
TEST=Built and booted on snow and ares.
Tested by setting and getting rate for MALI, Audio and FIMD

Change-Id: Id5fd517c2e2a2d93eae5f117e0ada5d67f5e5324
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56740
clk: samsung: pass clk->base instead of clk->con0 for PLL35xx on exynos5420

Passes clk->base instead of clk->con0 while registering exynos5420 PLLs

BUG=chrome-os-partner:19772
TEST=Built and booted on snow and ares.
Tested by setting and getting rate for MALI, Audio and FIMD

Change-Id: I73932825fb8a2b98c662c68a95b2700f808784ef
Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56935
ARM: EXYNOS5420: Add dt support for gsc and sysmmu-gsc

This patch adds G-Scaler devices to the DT device list.
Adds sysmmu nodes in dtsi and dt support
for gcalar sysmmus
Also, adds gsc & sysmmu-gsc clock entries as needed by ccf

BUG=chrome-os-partner:19204
TEST=Tested with MFC decoder+GSC csc app [1]

[1]http://git.infradead.org/users/kmpark/public-apps

Change-Id: I0245242ebf3e057337b5d9b1a298b4b85bd08a74
Signed-off-by: Shirish S <s.shirish@samsung.com>
Signed-off-by: Kiran AVND <avnd.kiran@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/56388
Reviewed-by: Pawel Osciak <posciak@chromium.org>
Tested-by: Pawel Osciak <posciak@chromium.org>
Commit-Queue: Doug Anderson <dianders@chromium.org>
ARM: exynos: Add support for samsung,mfc-v7 to mach-exynos5-dt board

On exynos5420 we've got v7 of the MFC core.  Modify the
mach-exynos5-dt board file to handle this new compatible string.

BUG=chrome-os-partner:19203
TEST=Tested with MFC decoder & encoder test app [1]
[1] http://git.infradead.org/users/kmpark/public-apps

[dianders split out device tree; cleaned up code a bit]

Change-Id: I199c572bd53a96dee632e455e2b236a21d9fff59
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: ARUN MANKUZHI <arun.m@samsung.com>
Signed-off-by: Kiran AVND <avnd.kiran@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56389
Reviewed-by: Pawel Osciak <posciak@chromium.org>
Tested-by: Pawel Osciak <posciak@chromium.org>
ARM: dts: Add mfc nodes for exynos5420 SoC

Hooks clocks, interrupts, etc up as per SoC User manual.

BUG=chrome-os-partner:19203
TEST=Tested with MFC decoder & encoder test app [1]
[1] http://git.infradead.org/users/kmpark/public-apps

Change-Id: Idcd6ef0c1ac42a3e0e8c0025f203fff409daa30f
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: ARUN MANKUZHI <arun.m@samsung.com>
Signed-off-by: Kiran AVND <avnd.kiran@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56852
Reviewed-by: Pawel Osciak <posciak@chromium.org>
Tested-by: Pawel Osciak <posciak@chromium.org>
ARM: dts: Add mfc node to smdk5420 dts file

This adds memory reservations for MFC that we'll use on smdk5420.

BUG=chrome-os-partner:19203
TEST=Tested with MFC decoder & encoder test app [1]
[1] http://git.infradead.org/users/kmpark/public-apps

Change-Id: I24c35e40d28f8ab9456e48471a7e2b690c1e474d
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: ARUN MANKUZHI <arun.m@samsung.com>
Signed-off-by: Kiran AVND <avnd.kiran@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56853
Reviewed-by: Pawel Osciak <posciak@chromium.org>
Tested-by: Pawel Osciak <posciak@chromium.org>
clk: assign parent to sysmmu clock for mfc,gsc

assign mfc as parent clock for sysmmu mfc_l and sysmmu mfc_r
Also, assign gsc0 as parent clock for sysmmu gsc0 and
gsc1 as parent clock for sysmmy gsc1

BUG=chrome-os-partner:19203, 19204
TEST=Tested with MFC decoder+GSC csc app [1]

[1]http://git.infradead.org/users/kmpark/public-apps

Change-Id: I501ee7a93626b5a2cb195b967dff76a92859d0ff
Signed-off-by: kiran AVND <avnd.kiran@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/56390
Reviewed-by: Pawel Osciak <posciak@chromium.org>
Tested-by: Pawel Osciak <posciak@chromium.org>
Commit-Queue: Doug Anderson <dianders@chromium.org>
ARM: dts: Add mfc node to the pit dts file

This adds memory reservations for MFC that we'll use on pit.

BUG=chrome-os-partner:19203
TEST=Tested with MFC decoder & encoder test app [1]
[1] http://git.infradead.org/users/kmpark/public-apps

Change-Id: Ic3261cc4781bd7526482feeacea92da6ca922e18
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56854
Reviewed-by: Pawel Osciak <posciak@chromium.org>
Tested-by: Pawel Osciak <posciak@chromium.org>
CHROMIUM: cros_ec: Remove unused member from struct cros_ec_device

The dev_lock member wasn't used anywhere. Locking is handled at a lower
level.

BUG=chromium:239197
BRANCH=all
TEST=manual

Built, booted. That mutex isn't used anywhere.

Original-Change-Id: Ia4daa7ac236c2f2a6f6562c2b3dec74531bf55bb
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit-int.chromium.org/38359
Commit-Queue: Simon Glass <sjg@google.com>
Reviewed-by: Simon Glass <sjg@google.com>
Tested-by: Simon Glass <sjg@google.com>
(cherry picked from commit 6343ee9189f313cd80ed1a21c802e5903892745d)

Change-Id: Ia5f46e1ec7c7a1914995073fda686afa29f8dd34
Reviewed-on: https://gerrit.chromium.org/gerrit/57051
Commit-Queue: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
CHROMIUM: cros_ec: Fix the comment on cros_ec_remove()

This comment was incorrect, so update it.

BUG=chromium:239197
BRANCH=all
TEST=build for pit

Original-Change-Id: Ie138692720ed818b142d458b5975a778d3f8926d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Updated commit message and removed erroneous free()
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit-int.chromium.org/38360
Commit-Queue: Simon Glass <sjg@google.com>
Reviewed-by: Simon Glass <sjg@google.com>
Tested-by: Simon Glass <sjg@google.com>
(cherry picked from commit 89f730f3edc56f0ad097fb169dd8908dd58a0208)

Change-Id: I51b22e5c885c609f8fc5fc32b936fb3c1049cc78
Reviewed-on: https://gerrit.chromium.org/gerrit/57054
Commit-Queue: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>