ASoC: ABE: Use DMA at 16-bits specifically for 16-bits mono

Use sDMA configured at 16-bits specifically for 16-bits mono.
Otherwise, use 32-bits as 16-bits stereo can be packed into
a 32-bits container.

Since the DMA data size is not fixed, it doesn't make sense
to keep it as part of the static DMA parameters anymore.

Change-Id: Ib38a0d77fc8dc0935fdf3e61e291a500b32865d2
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Merge branch 'android-3.0' into android-omap-3.0
Merge branch 'linux-omap-3.0' into android-omap-3.0
MFD: TWL 6030: clear IRQ status register only once

TWL6030 family of PMIC use a shadow interrupt status register
while kernel processes the current interrupt event.
However, any write(0 or 1) to register INT_STS_A, INT_STS_B or
INT_STS_C clears all 3 interrupt status registers.

Since clear of the interrupt is done on 32k clk, depending on I2C
bus speed, we could in-adverently clear the status of a interrupt
status pending on shadow register in the current implementation.
This is due to the fact that multi-byte i2c write operation into
three seperate status register could result in multiple load
and clear of status and result in lost interrupts.

Instead, doing a single byte write to INT_STS_A register with 0x0
will clear all three interrupt status registers without the related
risk.

Change-Id: Iba62dd1caeabf8c2db21d1b6c9fd62455f73205e
Signed-off-by: Nishanth Menon <nm@ti.com>
Merge branch 'linux-omap-3.0' into android-omap-3.0
Merge branch 'android-3.0' into android-omap-3.0
gpu: pvr: Update to DDK 1.8@808799

 - Fix a bad pointer dereference in services DC.
 - Correct GPL license text in two files.

Change-Id: Id5c4b3b2b3495007aa9a8e554f8ff8a69ebec500
Merge branch 'linux-omap-3.0' into android-omap-3.0
ARM: OMAP4: cpuidle: prevent CPU1 from locking CPU0 in idle entry

We can have a lockup scenario when two cpu are spin waiting for each other:

CPU0:
	omap4_enter_idle()
		|---omap4_enter_idle_primary()
			|---------while (omap4_idle_requested_cx[1])
					cpu_relax();

CPU1:
	omap4_enter_idle()
		|----
		while ((omap4_idle_ready_count == 0) && omap4_all_cpus_idle()) {
			spin_unlock(&omap4_idle_lock);
			cpu_relax();
			spin_lock(&omap4_idle_lock);
		}

Depend on idle ready count to let CPU0 to progress forward.

Change-Id: Ida6b60f618e8078701fcad8d976c3f1620cc71e6
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Yuan Jiangli <jlyuan@motorola.com>
Merge branch 'android-3.0' into android-omap-3.0
Merge branch 'linux-omap-3.0' into android-omap-3.0
gpu: pvr: Update to DDK 1.8@813213

 - Add PVRSRV_MMU_MAKE_READWRITE_ON_DEMAND feature for Crespo MapPage()
   crash bug investigation. This will write-protect the MMU pagetables
   when the SGX driver is not modifying them.

Change-Id: If2b488128ddf28536d6e706dc977f719c0193f61
gpu: pvr: Update to DDK 1.8@840215

Change-Id: I5e42b74681bb5ee14235f7ed227d4fe581a2d12e
Merge branch 'linux-omap-3.0' into android-omap-3.0
OMAP4: trim_quirks: Fix wrong implementation of erratum i684

OMAP4430 erratum i684:
Due to trimming program issue and a related architectural issue,
the LPDDR I/O and Smart I/O was not trimmed correctly on certain
OMAP4430 revisions. The default value in CONTROL_EFUSE_2 is not
correct and requires to be over-ridden by software.
Units with ProdID[51:50]=11 are not impacted by this issue.

Workaround:
For all affected OMAP4430 units, the value of CONTROL_EFUSE_2 must
be overwritten with 0x004E4000.

Current implementation impacts all OMAP4, hence the fix
restricts to implement the WA only for OMAP4430 affected units. The
wrong value overriden to SoCs not impacted such as OMAP4460 can
cause memory instability in samples as the override
trim value was purposed purely for erratum impacted samples.

Change-Id: I747181ce25eb2574e2b91b5a0a102c538f43b632
Signed-off-by: Konstantin Shlyakhovoy <x0155534@ti.com>
Merge branch 'android-3.0' into android-omap-3.0
Merge branch 'linux-omap-3.0' into android-omap-3.0
Merge branch 'android-3.0' into android-omap-3.0
Merge branch 'android-3.0' into android-omap-3.0
OMAP3+: Smartreflex: Fix interrupt disable sequence

With the current interrupt disable sequence, we disable IRQENABLE
followed by clearing of IRQSTATUS. With this sequence, we see, at
times CORE domain does not hit OFF mode during cold boot because
SR modules(Core/IVA/MPU domains) are stuck 'in transition'.

After the IRQ is cleared by writing the SR_xxx_IRQENABLE_CLR ,
the SW cannot read the interrupt status from IRQSTATUS register.
SW should have cleared all IRQ completely before disabling the
module. If the SW disable the module by the MODULEMODE bit
before clearing the IRQ status, the SR module is still in the
'In transition' mode.

Hence, the right sequence we have is write to IRQSTATUS register
to clear the interrupt, then write to IRQENABLE_CLR register to
disable the interrupt to ensure that no pending interrupts exist
in the system on disable of SmartReflex AVS block.

Change-Id: Ic0e3d9960ed9511769c3c25b2c71ff1e53bcc796
Reported-by: Honda Kenji <x0092217@ti.com>
Reported-by: Maki Tanaka <m-tanaka1@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Huzefa Kankroliwala <huzefank@ti.com>