R600/SI: Prefer SALU instructions for bit shift operations

All shift operations will be selected as SALU instructions and then
if necessary lowered to VALU instruction in the SIFixSGPRCopies pass.

This allows us to do more operations on the SALU which will improve
performance and is also required for implementing private memory
using indirect addressing, since the private memory pointers must stay
in the scalar registers.
R600/SI: Add support for i64 bitwise or
R600/SI: Add support for private address space load/store

Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.
Fix trailing whitespace in debug printing
Style fix.
Fix indentation
Add a comment
Make method static
R600/SI: Replace writes to SCC with VCC.

When replacing scalar operations with vector,
the wrong implicit output register was used.
R600/SI: Replace reads from SCC as well.
R600/SI: Fix assert when instruction has duplicate register operand.

Temporary fix by clobbering iterators.
R600/SI: Use worklist in moveToVALU and make non-recursive.

This is an improved fix for the repeated operand problem.
This somewhat changes the ordering of when operands are legalized,
but I think it's OK.
R600/SI: Remove redundant legalizeOperands call
R600/SI: Move patterns to match add / sub to scalar instructions
R600/SI: Specify S_ADD/S_SUB set SCC and add is commutable
R600/SI: Match adde/sube to S_ADDC_U32/S_SUBB_U32
R600/SI: Match addc to S_ADD_U32.

The carry always goes to SCC.
R600/SI: addc / adde i32 are legal
R600/SI: Implement add i64, but do not yet enable.

Test doesn't actually check the output. I need
to fix add i64 being matched for the addressing
calculations.
R600/SI: Fix extra defs of VCC / SCC.

Replacing them before wasn't right, since the VCCs
were newly added.