Merge branch 'v2.2' of github.com:fnoble/Swift-Nav-Code into v2.2

Conflicts:
	tests/acq/acq_test.c
Changes to allow test registers to be read and for program to be rerun
without disconnecting the black magic probe. The initial FPGA configuration
must be done without remote debugging, but after that the STM can be rerun
and reprogrammed without having to reconfigure/powercycle.
- Changed LED macros (colors were reversed)
- GPIOs to drive MAX pins PGM,NSHDN,NIDLE now initialized in max2769_setup()
- Added FPGA_DONE, FPGA_PROGRAM_B pins in swift_nap_setup routine
- Added swift_nap_configure() routine in swift_nap_io - shouldn't be called
  if using swdp_scan in gdb, use swift_nap_reset() instead. FPGA won't be
  able to configure if swdp scan has been done.
- swift_nap_setup() routine should now be called before rcc_clock_setup in
  main. swift_nap_setup() now does stuff in the following order:
  -- Set up FPGA_PROGRAM_B ouput (not doing currently, it seems when this
     is set up it gets strobed low and the FPGA tries to reconfigure? This
     is fine if not using swdp, but for now we are)
  -- Set up FPGA_DONE input
  -- Set up FPGA logic reset pin (currently TIM2CH3-PA2 in FPGA firmware
     b81ee69bc6a15fc8e72acade0085baf032247592). Current FPGA firmware
     resets the PLLs with a logic reset (was necessary to have PLLs lock
     again in successive runs of the STM program where the MAX pins (PGM,
     NIDLE,NSHDN) are not driven until max2769_setup() is called.
  -- If FPGA_DONE is not high (device has just been powered on), then
     wait for it to go high
  -- Do spi_setup() (had to be after FPGA_DONE goes high as the FPGA
     uses SPI2 to read configuration data from the flash)
  -- Do max2769_setup() -- This allows the frontend clock into the FPGA,
     which in turn feeds it into the STM
  -- Setup the timing strobe
  -- Setup the external interrupt
--After swift_nap_setup() is called, swift_nap_reset() is called and resets
  the FPGA's logic and PLLs.
--rcc_clock_setup is called, and will wait until it gets a legit clock from
  the FPGA
--This new main sequence is shown in nap_test_regs_test.c
--Added mnap_test_regs_test.c, which shows new start-up sequence and
  reads/writes new test registers (spi addr 254 and 255 in FPGA)
Merge branch 'v2.2' of https://github.com/cbeighley/Swift-Nav-Code into v2.2
Updating nap_test_regs_test to continuously test the registers and
report any errors.
Cast here is unnecessary
Moving the stack to the F4 core coupled memory to give us a cool 64K.
Updating linker script with sizes of F4 flash and ram.
Change python code to reflect new ETS4 namespace layout.
Restore unbuffered settings for printf and friends.
Reserve the last page of the flash memory for settings.
Update Makefile to link against the F4 version of libopencm3.
Add openocd config script for the v2.2 board.
Beginning work on code for saving settings to the stm flash.
The old "debug" pins are no longer available on the v2.2 hardware.
Setup an reset NAP before changing the clock over.
Adjusting clock settings, needs more attention.
Changing all headers from F2 to F4.

Plus some whitespace cleanup.
Adding MAX2769 register definitions.
Adding in definitions for MAX reserved bits there are set high.
Initial test of max register settings with new definitions.