lm3530: Add a toggle for the CABC PWM
msm: pm-8x60: Setup memory for save/restore cpu registers early

Cores can be offlined early in the boot cycle by certain kernel
drivers.
Ensure that the memory to save and restore the cpu registers is
ready and available early during the boot procedure.

CRs-Fixed: 460083
Change-Id: I925372f066386ceb1e85184d4c58863835c3e88e
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
msm: hotplug: wait for hotplug completion event from secondary core

Primary core has to wait for hotplug completion event from secondary
core to avoid race between ongoing hotplug and already queued online
event. This also prevent CPU_DEAD notifiers from executing before the
SPM has completed the collapse of the CPU. CPU DEAD notifiers executing
early have been attributed to MDD hardware block for the CPU being
turned off prematurely, resulting in crashes.
The patch also adds support for probing with device tree for 8974
targets.

Change-Id: Ibd35a7c56f42f156a643ca6d531509f019b2a3be
CRs-fixed: 438314
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
msm: pm-8x60: Use relative time for events

There is a bug when adjusting for event wakeups. The adjusted time
is being set in absolute mode incorrectly. Instead just use relative
times.

Without this core wakeups may not happen on time.

CRs-fixed: 486466
Change-Id: If625f25bd573b05befb6e0f922c80db646428b86
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
msm: pm: send notification only for SPC and PC

Today the pm notification is sent for all the power
modes of each CPU. This is not necessary for shallow
power modes.

This change is to send the notification for only
standalone power collapse for each core and idle
power collapse of core0.

Change-Id: I9b3df3d72e43d645387c94b1b9c5da3bcf2f2e5f
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
msm: cpufreq: increase priority of thread that increases frequencies

When the cpufreq governors request for increase in frequency from kworker
threads, there is chance that the kworker thread is cpu starved due to
other high priority threads, leading to undesirable increase in frequency
ramp-up latency. Add the calling thread to SCHED_FIFO policy when
requesting for increase in frequency and restore back to original policy
after ramp-up is completed.

Change-Id: Ie4fa199b7f9087717cb94dfcc2eddea27cc0012b
Signed-off-by: Narayanan Gopalakrishnan <nargop@codeaurora.org>
msm_fb: display: fix iommu page fault when iommu buffer freed

There has possibility that pipe commit come very close to next vsync.
This may cause two consecutive pipe_commits happen within same vsync
period which cause iommu page fault when previous iommu buffer is
freed since mdp stil fetching it. Set ION_IOMMU_UNMAP_DELAYED flag
at ion_map_iommu() to add delay un mapping iommu buffer to fix this problem.
Otherwise four buffer mechanism is needed to avoid this problem..
Also ion_unmap_iommu() may take long time to free an ion buffer. Move
mdp4_overlay_iommu_unmap_freelist(mixer) called after stage_commit()
to increase chance to have pipe_commit (up to stage_commit) is completed
within same vsync period
This patch also fix an potential race condition at wait_for_completion
between show_event thread and wait4vsync thread.

Change-Id: I673b0e368bbcd3120bc26569fe7a7bb82931daaa
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
(cherry picked from commit ada63be0fd32e729e4b91aeeea2a5cfe0830148c)
(cherry picked from commit 799796f15e0b78ffe47975db1cf7f3791cb98129)
msm: avs: Restore core voltage when disabling AVS

AVS changes the core voltage to match the current operating conditions
on the part. Not all frequencies supported by the target have characterized
AVS delay synthesizer (AVSDSCR) values. For frequencies that do not have
AVSDSCR set, AVS is not enabled and so need to operate at the
characterized voltage for that frequency. Disabling AVS does not
however, restore the operating voltage to the value the rail was
configured to. This may cause frequencies that do not have AVSDSCR to
run at lower voltage than prescibed.
Set up the core voltage back to the last known good value when disabling
AVS.

Change-Id: I5389996288fa49e45c469d2a8917e00900261de7
CRs-fixed: 457772
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
msm: spm: set vdd directly for current cpu

In cases where a cpu is setting vdd for itself we need not
call msm_spm_smp_set_vdd through smp_call_function_single.

Without this change when CPU calls for itself when interrupts
are disabled we get following warning

[ 38.407752] ------------[ cut here ]------------
[ 38.407752] WARNING: at kernel/kernel/smp.c:320
smp_call_function_single+0xa8/0x1c8()
[ 38.407752] Modules linked in: adsprpc
[ 38.407752] [<c00149b8>] (unwind_backtrace+0x0/0x11c) from [<c0082afc>]
(warn_slowpath_common+0x4c/0x64)
[ 38.407752] [<c0082afc>] (warn_slowpath_common+0x4c/0x64) from
[<c0082b2c>] (warn_slowpath_null+0x18/0x1c)
[ 38.407752] [<c0082b2c>] (warn_slowpath_null+0x18/0x1c) from
[<c00c510c>] (smp_call_function_single+0xa8/0x1c8)
[ 38.407752] [<c00c510c>] (smp_call_function_single+0xa8/0x1c8) from
[<c0058f6c>] (msm_spm_set_vdd+0x48/0x70)
[ 38.407752] [<c0058f6c>] (msm_spm_set_vdd+0x48/0x70) from [<c0056a98>]
(msm_pm_power_collapse+0x13c/0x334)
[ 38.407752] [<c0056a98>] (msm_pm_power_collapse+0x13c/0x334) from
[<c0057120>] (msm_pm_enter+0x170/0x2dc)
[ 38.407752] [<c0057120>] (msm_pm_enter+0x170/0x2dc) from [<c00b7580>]
(suspend_devices_and_enter+0x1d0/0x334)
[ 38.407752] [<c00b7580>] (suspend_devices_and_enter+0x1d0/0x334) from
[<c00b7800>] (pm_suspend+0x11c/0x1f8)
[ 38.407752] [<c00b7800>] (pm_suspend+0x11c/0x1f8) from [<c00b87a4>]
(suspend+0x68/0x180)
[ 38.407752] [<c00b87a4>] (suspend+0x68/0x180) from [<c009b050>]
(process_one_work+0x280/0x488)
[ 38.407752] [<c009b050>] (process_one_work+0x280/0x488) from
[<c009b46c>] (worker_thread+0x214/0x3b4)
[ 38.407752] [<c009b46c>] (worker_thread+0x214/0x3b4) from [<c009f364>]
(kthread+0x84/0x90)
[ 38.407752] [<c009f364>] (kthread+0x84/0x90) from [<c000f108>]
(kernel_thread_exit+0x0/0x8)
[ 38.407752] ---[ end trace da227214a82491ba ]---

Change-Id: I1aa121f57d74860b6bc8620b40699567e55a9d02
CRs-Fixed: 480408
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
msm: pm: Add support for retention on each core

Allow each core on 8974 to enter retention and retain
the state of the CPU. On 8960 as hardware restriction does
not permit all cores to enter retention at the same time,
allow only core 0 to enter retention when all other cores
are offline to maintain backward compatibility.

CRs-fixed: 437281
Change-Id: I6690e901afc9fa3a27010c264fa3acc9a0722c1a
Signed-off-by: Priyanka Mathur <pmathur@codeaurora.org>
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
msm: pm: add failed stats

for idle and suspend failed cases the stats
are not updated correctly, they are just added to
success bucket.

This patch is to log the failed stats separately.

Change-Id: I4b290944e3f4b74ada13ef0ba51b812c83b5ec5d
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
msm:rq_stats: Register for Cpufreq policy notification

Currently the load of the system is calculated using the max
frequency that is read during startup(It does not get updated
when the policy changes). As a result, the average load of the
system is incorrectly calculated and the system might not bring
the cpus online to manage the additional load. This
reduces the performance of the system.

To fix this issue, register rq_stats to receive cpufreq policy
notifications. Update the policy's max frequency when a
notification is received and use that value to calculate the load.

Change-Id: Icc78e28c736c170e198f723fd96c13dfb2dafe8a
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
msm: rpm: add debug msg for rpm outstanding req

added a debug info for showing the power collapse
abort due to rpm outstanding request.

Change-Id: Ifbc8054033b3cc86ccebc625b501ddb8b2670707
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
Staging: android: binder: Fix memory leak on thread/process exit

If a thread or process exited while a reply, one-way transaction or
death notification was pending, the struct holding the pending work
was leaked.

CRs-Fixed: 477612
Change-Id: I8b7a4f77689731a47c9e2f2fffefcac95c412e00
Signed-off-by: Arve Hjønnevåg <arve@android.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Git-commit: 675d66b0ed5fd170d6a44cf8dbb3fa56a5347bdb
Git-repo: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
msm: display: Add DSI clock control for MDP GDHS power collapse

Enable DSI clock and regulator before enabling/disabling power collapse
for MDP GDHS.

(cherry picked from commit ad3200279e62eff01fd1bb9136cc9c0d11e10380)

(cherry picked from commit 58c5992c710df379e26bb210e00c74da501db9d2)

Change-Id: I76b91260c61abf214e688c0dea6989ed2cfa3801
Signed-off-by: Ravishangar Kalyanam <rkalya@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/board-8064-regulator.c

Signed-off-by: Dhivya Subramanian <dthiru@codeaurora.org>
geeb: Add DSI clock control for MDP GDHS power collapse

Change-Id: I8dacd22467e53f472b65787749d632eb8de2bb89
msm: Fix race condition in domain lookup

During lookup of domains we take a pointer to the root node
of the rb tree before taking the mutex to protect the rb tree.
However, the rb root node might change if another process updates
the rb tree after we take the pointer to the root node. This can
cause us to not find the entry that we are looking for.
Fix this by ensuring we have taken the mutex before getting the
root node pointer.

CRs-fixed: 493503
Change-Id: I4702740e486fda0cd92df0401d8e4706598a899b
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
mmc: core: Allow changing bus frequency for SD/eMMC cards in runtime

Currently, bus frequency is set during the card initialization and
never changed until a new card is inserted. In some low power use
cases, scaling the clock frequencies while the card is in transfer
state would allow power savings. This change allows bus frequency
to be changed after the card initialization.

Change-Id: Iac064221199f69d162d91f5311becd735c15700a
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
mmc: core: Fix some driver hangs when dealing with broken devices

There are infinite loops in the mmc code that can be caused by bad
hardware.  The code will loop forever if the device never comes back
from program mode, R1_STATE_PRG, and it is not ready for data,
R1_READY_FOR_DATA.

A long timeout is added to prevent the code from looping forever.
The timeout will occur if the device never comes back from program
state or the device never becomes ready for data.

It's not clear whether the timeout will do more than log a pr_err()
and then start a fresh hang all over again.  We may need to extend
this patch later to perform some kind of reset of the device (is
that possible?) or rejection of new I/O to the device.

Change-Id: I1f3e5fddffb5134743fbfbcdef5e97803fd25fc6
Signed-off-by: Trey Ramsay <tramsay@linux.vnet.ibm.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
mmc: core: Add load based clock scaling support

The SD3.0/eMMC4.5/SDIO3.0 cards can support clock rates upto
200MHz (SDR104 or HS200 bus speed modes). For some workloads
like video playback it isn't necessary for these cards to run
at such high speed. Running at lower frequency, say 50MHz, in
such cases can still meet the deadlines for data transfers.
Scaling down the clock frequency dynamically has huge power
savings not only because the bus is running at lower frequency
but also has an advantage of scaling down the system core
voltage, if supported.

Provide an ondemand clock scaling support similar to cpufreq
ondemand governor having two thresholds, up_threshold and
down_threshold to decide whether to increase the frequency or
scale it down respectively. The sampling interval is in the
order of milliseconds and should be chosen by host drivers that
enable MMC_CAP2_CLK_SCALE capability to take advantage of clock
scaling. The sampling interval mainly depends on the the clock
switching delays and hence a host driver decision. If sampling
interval is too low frequent switching of frequencies can lead
to high power consumption and if sampling interval is too high,
the clock scaling logic would take long time to realize that the
underlying hardware (controller and card) is busy and scale up
the clocks.

Change-Id: I22a5054beec41b0b66b3bf030ddfcf284de448b3
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>