[FIX] Add enable port to DPRAM library components

- Add enable port to each port.
- Fix init file assert in Xilinx architecture.

Change-Id: Ib55399e00040c94beea9c31817d2aed0ec7da67e
Reviewed-on: http://brateggevoat1/gerrit/1435
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>